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8 bit microcontroller tlcs-870/x series TMP88PH40MG

revision history date revision 2007/7/10 1 first release

i table of contents TMP88PH40MG 1.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.2 pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.3 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.4 pin names and functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2. functional description 2.1 functions of the cpu core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.1.1 memory address map ............................................................................................................................... 7 2.1.2 program memory (rom) .......................................................................................................................... 8 2.1.3 data memory (ram) ............................................................................................................................... .. 8 2.1.4 system clock control circuit .................................................................................................................... 9 2.1.4.1 clock generator 2.1.4.2 timing generator 2.1.4.3 standby control circuit 2.1.4.4 controlling operation modes 2.1.5 reset circuit ............................................................................................................................... ............ 17 2.1.5.1 external reset input 2.1.5.2 adress trap reset 2.1.5.3 watchdog timer reset 2.1.5.4 system clock reset 3. interrupt control circuit 3.1 interrupt latches (il38 to il2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.2 interrupt enable register (eir) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.2.1 interrupt master enable flag (imf) .......................................................................................................... 21 3.2.2 individual interrupt enable flags (ef38 to ef3) ...................................................................................... 21 3.3 interrupt sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.3.1 interrupt acceptance processing is packaged as follows. ....................................................................... 24 3.3.2 saving/restoring general-purpose registers ............................................................................................ 25 3.3.2.1 using automatic register bank switcing 3.3.2.2 using register bank switching 3.3.2.3 using push and pop instructions 3.3.2.4 using data transfer instructions 3.3.3 interrupt return ............................................................................................................................... ......... 27 3.4 software interrupt (intsw) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 3.4.1 address error detection .......................................................................................................................... 28 3.4.2 debugging ............................................................................................................................... ............... 28 3.5 external interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 4. special function register 4.1 sfr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 4.2 dbr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
ii 5. input/output ports 5.1 port p1 (only p10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 5.2 port p3 (p37 to p30) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 5.3 port p4 (p45 to p40) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 5.4 port p6 (p63 to p60) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 6. watchdog timer (wdt) 6.1 watchdog timer configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 6.2 watchdog timer control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 6.2.1 malfunction detection methods using the watchdog timer ................................................................... 42 6.2.2 watchdog timer enable ......................................................................................................................... 43 6.2.3 watchdog timer disable ........................................................................................................................ 44 6.2.4 watchdog timer interrupt (intwdt) ...................................................................................................... 44 6.2.5 watchdog timer reset ........................................................................................................................... 45 7. time base timer (tbt) 7.1 time base timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 table 7-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 8. 16-bit timercounter 1 (tc1) 8.1 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 8.2 timercounter control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 8.3 function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 8.3.1 timer mode ............................................................................................................................... .............. 51 figure 8-2 ................................................................................................................. ....................................... 52 figure 8-2 ................................................................................................................. ....................................... 52 figure 8-2 ................................................................................................................. ....................................... 52 figure 8-2 ................................................................................................................. ....................................... 52 figure 8-2 ................................................................................................................. ....................................... 52 9. 8-bit timercounter 3 (tc3) 9.1 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 9.2 timercounter control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 9.3 function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 9.3.1 timer mode ............................................................................................................................... .............. 55 figure 9-3 ................................................................................................................. ....................................... 56 figure 9-3 ................................................................................................................. ....................................... 56 10. 8-bit timercounter 4 (tc4) 10.1 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 10.2 timercounter control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 10.3 function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
iii 10.3.1 timer mode ............................................................................................................................... ............ 59 table 10-1 ................................................................................................................. ...................................... 59 table 10-1 ................................................................................................................. ...................................... 59 11. motor control circuit (pmd: programmable motor driver) 11.1 outline of motor control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 11.2 configuration of the motor control circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 11.3 position detection unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 11.3.1 configuration of the position detection unit ........................................................................................... 66 11.3.2 position detection circ uit register functions ....................................................................................... 67 11.3.3 outline processing in the position detection unit ................................................................................ 70 11.4 timer unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 11.4.1 configuration of the timer unit ............................................................................................................. 72 11.4.1.1 timer circuit register functions 11.4.1.2 outline processing in the timer unit 11.5 three-phase pwm output unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 11.5.1 configuration of the three-phase pwm output unit ............................................................................... 76 11.5.1.1 pulse width modulation circuit (pwm waveform generating unit) 11.5.1.2 commutation control circuit 11.5.2 register functions of the waveform synthesis circuit ......................................................................... 80 11.5.3 port output as set with uoc/voc/ woc bits and upwm/vpwm/wpwm bits ..................................... 82 11.5.4 protective circuit ............................................................................................................................... .... 84 11.5.5 functions of protective circuit registers .............................................................................................. 86 11.6 electrical angle timer and waveform arithmetic circuit . . . . . . . . . . . . . . . . . . . 88 11.6.1 electrical angle timer and wa veform arithmetic circuit ...................................................................... 89 11.6.1.1 functions of the electrical angle timer and waveform arithmetic circuit registers 11.6.1.2 list of pmd related control registers 12. asynchronous serial interface (uart) 12.1 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 12.2 control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 12.3 transfer data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 12.4 transfer rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 12.5 data sampling method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 12.6 stop bit length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 12.7 parity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 12.8 transmit/receive operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 12.8.1 data transmit operation .................................................................................................................... 106 12.8.2 data receive operation ..................................................................................................................... 106 12.9 status flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 12.9.1 parity error ............................................................................................................................... ........... 107 12.9.2 framing error ............................................................................................................................... ....... 107 12.9.3 overrun error ............................................................................................................................... ....... 107 12.9.4 receive data buffer full ..................................................................................................................... 108 12.9.5 transmit data buffer empty ............................................................................................................... 108 12.9.6 transmit end flag .............................................................................................................................. 109 13. synchronous serial interface (sio) 13.1 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 13.2 control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 13.3 serial clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 13.3.1 clock source ............................................................................................................................... ........ 113
iv 13.3.1.1 internal clock 13.3.1.2 external clock 13.3.2 shift edge ............................................................................................................................... ............. 115 13.3.2.1 leading edge 13.3.2.2 trailing edge 13.4 number of bits to transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 13.5 number of words to transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 13.6 transfer mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 13.6.1 4-bit and 8-bit transfer modes ............................................................................................................. 116 13.6.2 4-bit and 8-bit receive modes ............................................................................................................. 118 13.6.3 8-bit transfer / receive mode ............................................................................................................... 119 14. 10-bit ad converter (adc) 14.1 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 14.2 register configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 14.3 function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 14.3.1 software start mode ........................................................................................................................... 125 14.3.2 repeat mode ............................................................................................................................... ....... 125 14.3.3 register setting ............................................................................................................................... . 126 14.4 analog input voltage and ad conversion result . . . . . . . . . . . . . . . . . . . . . . . 128 14.5 precautions about ad converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 14.5.1 analog input pin voltage range ........................................................................................................... 129 14.5.2 analog input shared pins .................................................................................................................... 129 14.5.3 noise countermeasure ....................................................................................................................... 129 15. otp operation 15.1 operating mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 15.1.1 mcu mode ............................................................................................................................... ........... 131 15.1.1.1 program memory 15.1.1.2 data memory 15.1.1.3 input/output circuiry 15.1.2 prom mode ............................................................................................................................... ........ 132 15.1.2.1 programming flowchart (high-speed program writing) 15.1.2.2 program writing using a general-purpose prom programmer 16. input/output circuitry 16.1 control pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 16.2 input/output ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 17. electrical characteristics 17.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 17.2 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 17.3 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 17.4 ad conversion characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 17.5 ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 17.6 dc characteristics, ac characteristics (prom mode) . . . . . . . . . . . . . . . . . . . 142 17.6.1 read operation in prom mode .......................................................................................................... 142 17.6.2 program operation (high-speed) ........................................................................................................ 143 17.7 recommended oscillation conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
v 17.8 handling precaution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 18. package dimensions this is a technical docu ment that describes the operat ing functions and electrical specifications of the 8-bit microc ontroller series tlcs-870/x (lsi).
vi

page 3 TMP88PH40MG 1.2 pin assignment figure 1-1 pin assignment 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 vss xout test vdd reset (z1) p30 (y1) p31 (x1) p32 (w1) p33 (v1) p34 xin (u1) p35 ( cl1 ) p37 ( emg1 ) p36 p41 (pdv1) p43 ( sck ) p44 (si/rxd) p45 (so/txd) p10 ( int0 ) p42 (pdu1) avdd avss varef p62 ain2 p61 ain1 p60 ain0 p63 (ain3/dbout1) p40 (pdw1)
page 4 1.3 block diagram TMP88PH40MG 1.3 block diagram figure 1-2 block diagram
page 5 TMP88PH40MG 1.4 pin names and functions the TMP88PH40MG has mcu mode and prom mode. table 1-1 shows the pin functions in mcu mode. the prom mode is explained later in a separate chapter. table 1-1 pin names and functions(1/2) pin name pin number input/output functions p10 int0 21 io i port10 external interrupt 0 input p37 cl1 14 io i port37 pmd over load protection input1 p36 emg1 13 io i port36 pmd emergency stop input1 p35 u1 12 io o port35 pmd control output u1 p34 v1 11 io o port34 pmd control output v1 p33 w1 10 io o port33 pmd control output w1 p32 x1 9 io o port32 pmd control output x1 p31 y1 8 io o port31 pmd control output y1 p30 z1 7 io o port30 pmd control output z1 p45 so txd 20 io o o port45 serial data output uart data output p44 si rxd 19 io i i port44 serial data input uart data input p43 sck 18 io io port43 serial clock i/o p42 pdu1 17 io i port42 pmd control input u1 p41 pdv1 16 io i port41 pmd control input v1 p40 pdw1 15 io i port40 pmd control input w1 p63 ain3 dbout1 25 io i o port63 analog input3 pmd debug output1 p62 ain2 24 io i port62 analog input2 p61 ain1 23 io i port61 analog input1 p60 ain0 22 io i port60 analog input0 xin 2 i resonator connecting pins for high-frequency clock
page 6 1.4 pin names and functions TMP88PH40MG xout 3 o resonator connecting pins for high-frequency clock reset 6 i reset signal test 4 i test pin for out-going test and the serial prom mode control pin. usually fix to low level. fix to high level when the serial prom mode starts. varef 26 i analog base voltage input pin for a/d conversion avdd 27 i analog power supply avss 28 i analog power supply vdd 5 i +5v vss 1 i 0(gnd) table 1-1 pin names and functions(2/2) pin name pin number input/output functions
page 7 TMP88PH40MG 2. functional description 2.1 functions of the cpu core the cpu core consists mainly of the cpu, system clock control circuit, and interrupt control circuit. this chapter describes the cpu core, program memory, data memory, and reset circuit of the TMP88PH40MG. 2.1.1 memory address map the memory of the TMP88PH40MG consists of four blocks: rom, ram, sfr (special function regis- ters), and dbr (data buffer registers), which are ma pped into one 1-mbyte addr ess space. the general-pur- pose registers consist of 16 banks, which are mapped into the ram addr ess space. figure 2-1 shows a memory address map of the TMP88PH40MG . figure 2-1 memory address map vector table for vector call instructions interrupt vector table interrupt vector table program memory rom ( kbytes) ram ( bytes) ram (128 bytes) sfr rom: read-only memory program memory vector table sfr: special function registers input/output port peripheral hardware control register peripheral hardware status register system control register interrupt control register program status word dbr: data buffer registers input/output port peripheral hardware control registe r peripheral hardware status register ram: random access memory data memory stack general-purpose register bank random-access memory special function register general-purpose register bank (8 registers 16 banks) data buffer register (peripheral hardware control register / status register) 64 bytes 64 bytes 64 bytes 128 bytes bytes bytes 128 bytes 00000h 000c0h 000bfh 04000h 0003fh 00040h 01fffh fffffh fff7fh fff80h fff40h fff00h fff3fh bytes 512 512 16k 16128 dbr 01f80h 07effh 002bfh 128
page 8 2. functional description 2.1 functions of the cpu core TMP88PH40MG 2.1.2 program memory (rom) the TMP88PH40MG contains 16kbytes program memory (otp) located at addresses 04000h to 07effh and addresses fff00h to fffffh. 2.1.3 data memory (ram) the TMP88PH40MG contains 512bytes +128bytes ram. the first 128bytes location (00040h to 000bfh) of the internal ram is shared wi th a general-purpose register bank. the content of the data memory is indeterminate at power-on, so be sure to initialize it in the initialize rou- tine . note:because general-purpose registers exist in the ra m, never clear the current bank address of ram. in the above example, the ram is cleared except bank 0. example :clearing the inte rnal ram of the TMP88PH40MG (clear al l ram addresses to 0, except bank 0) ld hl, 0048h ; set the start address ld a, 00h ; set the initialization data (00h) ld bc, 277h ; set byte counts (-1) sramclr: ld (hl+), a dec bc jrs f, sramclr
page 9 TMP88PH40MG 2.1.4 system clock control circuit the system clock control circuit consists of a clock generator, timing generator, and standby control cir- cuit. figure 2-2 system clock control circuit 2.1.4.1 clock generator the clock generator generates the fundamental clock which serves as the reference for the system clocks supplied to the cpu core and peripheral hardware units. the high-frequency clock (frequency fc) can be obtai ned easily by connecting a resonator to the xin and xout pins. or a clock generated by an external os cillator can also be used. in this case, enter the external clock from the xin pin and leave the xout pin open. the TMP88PH40MG does not support the cr network that produces a time constant. figure 2-3 example fo r connecting a resonator adjusting the oscillation frequency note: although no hardware functions are provided that a llow the fundamental clock to be monitored directly from the outside, the oscillation frequency can be adjus ted by forwarding the pulse of a fixed frequency (e.g., clock output) to a port and monitoring it in a program while interrupts and the watchdog timer are disabled. for systems that require adjusting the os cillation frequency, an adjustment program must be created beforehand. 2.1.4.2 timing generator the timing generator generates various system cloc ks from the fundamental clock that are supplied to the cpu core and peripheral hardware units. the timing generator has the following functions: timing generator standby control circuit high-frequency clock oscillator circuit tbtcr syscr2 xin xout clock generator fc 00036h 00039h system clocks timing generator control register system control register xin high-frequency clock xout (a) using a crystal or ceramic resonator xin xout (b) using an external oscillator (open)
page 10 2. functional description 2.1 functions of the cpu core TMP88PH40MG 1. generate the source clock for the time base timer 2. generate the source clock for the watchdog timer 3. generate the internal source clock for the timer counter (1) configuration of the timing generator the timing generator a 3-stage prescaler, 21-st age dividers, and a machine cycle counter. when reset, the prescaler an d dividers are cleared to 0. figure 2-4 configuration of the timing generator dv1ck fc prescaler divider divider selector timer counter machine cycle counter 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 s a y b 6 5 4 3 2 1 1 2 0 standby control circuit watchdog timer time base timer
page 11 TMP88PH40MG note 1: fc: the high-frequency clock [hz], *: don?t care note 2: the cgcr register bits 4 and 3 show an indeterminate value when read. note 3: be sure to write ?0? to cgcr register bits 7, 6, 2, 1 and 0. (2) machine cycle instruction execution and the intern al hardware operations are sync hronized to the system clocks. the minimum unit of instruction execution is re ferred to as the ?mgmachine cycle?. the tlcs- 870/x series has 15 types of instructions, from 1-cycle instructions wh ich are executed in one machine cycle up to 15-cycle in structions that require a ma ximum of 15 m achine cycles. a machine cycle consists of four states (s0 to s3), with each st ate comprised of one main system clock cycle. figure 2-5 machine cycles divider control register cgcr (0030h) 76543210 0 0 dv1ck 0 0 0 (initial value: 000* *000) dv1ck selects input clock to the first divider stage 0: fc/4 1: fc/8 r/w main system clock states s0 s1 s2 s3 s0 s1 s2 s3 1/fc (0.20 s at 20 mhz) machine cycle
page 12 2. functional description 2.1 functions of the cpu core TMP88PH40MG 2.1.4.3 standby control circuit the standby control circuit starts/stops the high-fre quency clock oscillator ci rcuit and selects the main system clock. the system control registers (syscr2) are used to co ntrol operation modes of this cir- cuit. figure 2-6 shows an operation mode transition diagram, followed by description of the system con- trol registers. (1) single clock mode only the high-frequency clock osci llator circuit is used. because the main system clock is gener- ated from the high-frequency clock, the machin e cycle time in single clock mode is 4/fc [s]. 1. normal mode in this mode, the cpu core and peripheral hardware units are opera ted with the high-fre- quency clock. the TMP88PH40MG ente rs this normal mode after reset. 2. idle mode in this mode, the cpu and watchdog timer ar e turned off while the peripheral hardware units are operated with the hi gh-frequency clock. idle mode is entered into by using system control register 2. the device is placed out of this mode and back into normal mode by an interrupt from the peripheral hardware or an external interrupt. wh en imf (interrupt mas- ter enable flag) = 1 (interrupt enabled), the de vice returns to normal op eration after the inter- rupt has been serviced. when imf = 0 (interr upt disabled), the devi ce restarts execution beginning with the instruction next to one that placed it in idle mode. figure 2-6 operation mode transition diagram table 2-1 single clock mode operation mode oscillator circuit cpu core peripheral circuit machine cycle time high frequency low frequency single clock reset oscillate - reset reset 4/fc [s] normal operate operate idle stop reset normal mode idle mode interrupt instruction reset deasserted
page 13 TMP88PH40MG note 1: be sure to set "1" to syscr2 register bit7 . when it is cleared to 0, the device is reset. note 2: wdt: watchdog timer, *: don?t care note 3: be sure to write "0" to syscr2 register bit6 and bit5. note 4: the values of the syscr2 register bits 3 to 0 are indeterminate when read. 2.1.4.4 controlling operation modes (1) idle mode idle mode is controlled by system control re gister 2 (syscr2) and a maskable interrupt. dur- ing idle mode, the device retains the following state. 1. the cpu and watchdog timer stop operating. the peripheral hardware continues operating. 2. the data memory, register, program status word, and port output latch hold the state in which they were immediately before entering idle mode. 3. the program counter holds the instruction ad dress two instructions ahead the one that placed the device in idle mode. system control register 2 syscr2 (0039h) 76543210 1 0 0 idle (initial value: 1000 ****) idle place the device in idle mode 0: keep the cpu and wdt operating 1: stop the cpu and wdt (idle mode entered) r/w example :placing the device in idle mode set (syscr2) . 4
page 14 2. functional description 2.1 functions of the cpu core TMP88PH40MG figure 2-7 idle mode place the device in idle mode (by instruction) stop the cpu and wdt interrupt handling execute the instruction next to one that placed device idle mode reset ye s no no no interrupt request ? imf = 1 reset input ? ye s yes (released by interrupt) (released normally)
page 15 TMP88PH40MG the device can be released from id le mode normally or by an interr upt as selected with the inter- rupt master enable flag (imf). a. released normally (when imf = 0) the device can be released from idle mode by the interrupt source enabled by the inter- rupt individual enable flag (e f), and restarts execution beginning with the instruction next to one that placed it in idle mode. the interrupt latc h (il) for the interrupt source used to exit idle mode normally needs to be clear ed to 0 using a load instruction. b. released by interrupt (when imf = 1) the device can be released from idle mode by the interrupt source enabled by the inter- rupt individual enable flag (e f), and enters interrupt handling. after interrupt handling, the device returns to the instruction next to one that placed it in idle mode. the device can also be released from idle mode by pulling the reset pin input low, in which case the device is immediately reset as is normally reset by reset . after reset, the device starts oper- ating from normal mode. note: if a watchdog timer interrupt occurs immedi ately before entering idle mode, the device pro- cesses the watchdog timer interrupt without entering idle mode.
page 16 2. functional description 2.1 functions of the cpu core TMP88PH40MG figure 2-8 entering a nd exiting idle mode (b) exiting idle mode (a) entering idle mode (example: entered into by the set instruction placed at address a) idle a + 2 a + 3 set (syscr2). 4 operating 1. released normally idle idle a + 3 a + 4 instruction at address a + 2 operating 2. released by interrupt idle idle a + 3 interrupt accepted operating main system clock interrupt request program counter instruction execution main system clock interrupt request program counter instruction execution watchdog timer main system clock interrupt request program counter instruction execution watchdog timer watchdog timer
page 17 TMP88PH40MG 2.1.5 reset circuit the TMP88PH40MG has four ways to generate a reset: external reset input, address trap reset, watchdog timer reset, or system clock reset. table 2-2 shows how the internal hardware is initialized by reset operation. at power-on time, the internal cause reset circuits (watch dog timer reset, address trap reset, and system clock reset) are not initialized. 2.1.5.1 external reset input the reset pin is a hysteresis input with a pull-up resistor included. by holding the reset pin low for at least three machine cycles (12/fc [s]) or more while the power supply voltage is within the rated operat- ing voltage range and the oscillator is oscillating stably, the device is reset and its internal state is initial- ized. when the reset pin input is released back high, the device is freed from reset and starts executing the program beginning with the vector addre ss stored at addresses ffffch to ffffeh. figure 2-9 reset circuit 2.1.5.2 adress trap reset if the cpu should start looping for reasons of noise, etc. and attempts to fetch instructions from the internal ram,sfr or dbr area, the de vice generats an internal reset. the addess trap permission/prohibition is set by the address trap reset contro l register (atas,atkey). the address trap is permited initially and the inte rnal reset is generated by fetching from internal ram,sfr or dbr area. if th e address trap is prohibit ed, instructions in the internal ram area can be executed. table 2-2 internal hardware in itialization by reset operation internal hardware initial value i nternal hardware initial value program counter (pc) (ffffeh to ffffch) prescaler and divider for the timing generator 0 stack pointer (sp) not initialized general-purpose registers (w, a, b, c, d, e, h, l) not initialized register bank selector (rbs) 0 watchdog timer enable jump status flag (jf) 1 zero flag (zf) not initialized output latch of input/output port see description of each input/output port. carry flag (cf) not initialized half carry flag (hf) not initialized sign flag (sf) not initialized overflow flag (vf) not initialized interrupt master enable flag (imf) 0 interrupt individual enable flag (ef) 0 control register see description of each control register. interrupt latch (il) 0 interrupt nesting flag (inf) 0 ram not initialized reset input vdd reset
page 18 2. functional description 2.1 functions of the cpu core TMP88PH40MG note: read-modify-write instructions, such as a bit manipulat ion, cannot access atas or atkey register because these register are write only. note 1: in development tools, address trap cannot be pr ohibited in the internal ram,sfr or dbr area with the address trap control registers. when using dev elopment tools, even if the address trap permis- sion/prohibition setting is changed in the user?s pr ogram, this change is ineffective. to execute instructions from the ram area, development tools must be set accordingly. note 2: while the swi instruction at an address imm ediately before the address trap area is executing, the program counter is incremented to point to the next address in the address trap area; an address trap is therefore taken immediately. development tool setting ? to prohibit the address trap: 1. modify the iram (mapping attribute) area to (00040h to 000bfh) in the memory map win- dow. 2. set 000c0h to "address trap prohibition ar ea" as a new eram (mapping attribute) area. 3. load the user program 4. execute the address trap prohibition code in the user?s program 2.1.5.3 watchdog timer reset refer to the section ?watchdog timer.? 2.1.5.4 system clock reset when syscr2 register bit 7 is clear ed to 0, the system clock is turn ed off, causing the cpu to become locked up. to prevent this problem, upon detecting "0" to syscr2 register bit 7 or detecting "1" to syscr2 register bit 5, the device automatically generate s an internal reset signal to let the system clock continue oscillating. address trap control register atas (1f94h) 76543210 -------atas(initial value: **** ***0) atas select the address trap permission / prohibition 0: permit address trap 1: prohibit address trap (it may be available after setting control code for atkey register) write only address trap control code register atkey (1f95h) 76543210 (initial value: **** ****) atkey write control code to prohibit address trap d2h: address trap prohibition code others: ineffective write only
page 19 TMP88PH40MG 3. interrupt control circuit the TMP88PH40MG has a total of 19 interrupt sources excl uding reset. interrupts can be nested with priorities. two of the internal interrupt sources are pseudo nonmaskable while the rest are maskable. interrupt sources are provided with interrupt latches (il) , which hold interrupt requests, and independent vectors. the interrupt latch is set to ?1? by th e generation of its interrupt request wh ich requests the cpu to accept its inter- rupts. interrupts are enabled or disabled by software using the interrupt master enable fl ag (imf) and in terrupt enable flag (ef). if more than one interrupts are generated simultaneously, interrup ts are accepted in order which is domi- nated by hardware. however, there are no prioritized interrupt factors among non-maskable interrupts. interrupt factors enable condition interrupt latch vector address priority internal/external (reset) nonmaskable ? ffffc high 0 internal intsw (software interrupt) pseudo nonmaskable ? ffff8 1 internal intwdt (watchdog timer interrupt) pseudo nonmaskable il2 ffff4 2 external int0 (external interrupt 0) imf? ef3 = 1, int0en = 1 il3 ffff0 3 - reserved imf? ef4 = 1 il4 fffec 4 - reserved imf? ef5 = 1 il5 fffe8 5 internal inttbt (tbt interrupt) imf? ef6 = 1 il6 fffe4 6 - reserved imf? ef7 = 1 il7 fffe0 7 internal intemg1 (ch1 error detect interrupt) imf? ef8 = 1 il8 fffdc 8 - reserved imf? ef9 = 1 il9 fffd8 9 internal intclm1 (ch1 overload protection interrupt) imf? ef10 = 1 il10 fffd4 10 - reserved imf? ef11 = 1 il11 fffd0 11 internal inttmr31 (ch1 timer 3 interrupt) imf? ef12 = 1 il12 fffcc 12 - reserved imf? ef13 = 1 il13 fffc8 13 - reserved imf? ef14 = 1 il14 fffc4 14 - reserved imf? ef15 = 1 il15 fffc0 15 internal intpdc1 (ch1 posision detect interrupt) imf? ef16 = 1 il16 fffbc 16 - reserved imf? ef17 = 1 il17 fffb8 17 internal intpwm1 (ch1 waveform generater interrupt) imf? ef18 = 1 il18 fffb4 18 - reserved imf? ef19 = 1 il19 fffb0 19 internal intedt1 (ch1 erectric angle timer interrupt) imf? ef20 = 1 il20 fffac 20 - reserved imf? ef21 = 1 il21 fffa8 21 internal inttmr11 (ch1 timer1 interrupt) imf? ef22 = 1 il22 fffa4 22 - reserved imf? ef23 = 1 il23 fffa0 23 internal inttmr21 (ch1 timer2 interrupt) imf? ef24 = 1 il24 fff9c 24 - reserved imf? ef25 = 1 il25 fff98 25 internal inttc1 (tc1 interrupt) imf? ef26 = 1 il26 fff94 26 - reserved imf? ef27 = 1 il27 fff90 27 - reserved imf? ef28 = 1 il28 fff8c 28 - reserved imf? ef29 = 1 il29 fff88 29 - reserved imf? ef30 = 1 il30 fff84 30 - reserved imf? ef31 = 1 il31 fff80 31 internal intrx (uart receive interrupt) imf? ef32 = 1 il32 fff3c 32 internal inttx (uart transmit interrupt) imf? ef33 = 1 il33 fff38 33 internal intsio (sio interrupt) imf? ef34 = 1 il34 fff34 34 internal inttc3 (tc3 interrupt) imf? ef35= 1 il35 fff30 35 internal inttc4 (tc4 interrupt) imf? ef36 = 1 il36 fff2c 36 - reserved imf? ef37 = 1 il37 fff28 37 internal intadc (a/d converter interrupt) imf? ef38 = 1 il38 fff24 low 38
page 20 3. interrupt control circuit 3.1 interrupt latches (il38 to il2) TMP88PH40MG note 1: to use the watchdog timer interrupt (intwdt), clear wdtcr1 to "0" (it is set for the "reset request" after reset is released). it is described in t he section "watchdog timer" for details. 3.1 interrupt latches (il38 to il2) an interrupt latch is provided for eac h interrupt source, except for a software interrupt and an executed the unde- fined instruction interrupt. when interrupt request is genera ted, the latch is set to ?1?, and the cpu is requested to accept the interrupt if its interrupt is enabled. the interrupt latch is cleared to "0" immediately after accepting inter- rupt. all interrupt latches are initialized to ?0? during reset. the interrupt latches are located on address 003ch, 0 03dh, 002eh, 002fh and 002bh in sfr area. each latch can be cleared to "0" individually by instruction. however, il2 and il3 should not be cleared to "0" by software. for clearing the interrupt latch, load instruction should be used and then il2 should be set to "1". if the read-modify- write instructions such as bit manipulation or operation instructions are used, interrupt request would be cleared inadequately if interrupt is requeste d while such instructions are executed. since interrupt latches can be read, the status for interrupt requests can be monitored by software. but interrupt latches are not set to ?1? by an instruction. note: in main program, before manipulating the interrupt enable flag (ef) or the interrupt latch (il), be sure to clear imf to "0" (disable interrupt by di instruction). then set imf new ly again as required after operating on the ef or il (enable interrupt by ei instruction) in interrupt service routine, because the imf becomes "0 " automatically, clearing imf need not execute normally on interrupt service routine. however, if using multiple inte rrupt on interrupt service routine, manipulating ef or il should be executed before setting imf="1". example 1 :clears interrupt latches di ; imf 0 ld (ill), 111010000011 1111b ; il2 to il7 0 ld (ilh), 1110100000 111111b ; il8 to il15 0 ld (ile), 1110100000111111b ; il16 to il23 0 ld (ild), 1110100000 111111b ; il24 to il31 0 ld (ilc), 1110100000 111111b ; il32 toil38 0 ei ; imf 1 example 2 :reads interrupt latches ld wa, (ill) ; w (ilh), a (ill) ld bc, (ile) ; b (ild), c (ile) ld d, (ilc) ; d (ilc) example 3 :tests interrupt latches test (ill). 7 ; if il7 = 1 then jump jr f, sset
page 21 TMP88PH40MG 3.2 interrupt enab le register (eir) the interrupt enable register (eir) enables and disabl es the acceptance of interrupts, except for the pseudo non- maskable interrupts (software interrupt, undefined instru ction interrupt, address trap interrupt and watchdog inter- rupt). pseudo non-maskable interrupt is accep ted regardless of the contents of the eir. the eir consists of an interrupt mast er enable flag (imf) and the individua l interrupt enable flags (ef). these registers are located on address 003a h, 003bh, 002ch, 002dh and 002ah in sf r area, and they can be read and written by an instructions (including read-modify-write in structions such as bit manipulation or operation instruc- tions). 3.2.1 interrupt ma ster enable flag (imf) the interrupt enable register (imf ) enables and disables the acceptance of the whole maskable interrupt. while imf = ?0?, all maskable interrupts are not accepted regardless of the status on each individual interrupt enable flag (ef). by setting imf to ?1?, the inte rrupt becomes acceptable if th e individuals are enabled. when an interrupt is accepted, imf is cleared to ?0? after the latest st atus on imf is stacked. thus the maskable interrupts which follow are disabled temporarily . imf flag is set to "1" by the maskable interrupt return instruction [reti] after execu ting the interrupt service program r outine, and mcu can accept the inter- rupt again. the latest interrupt request is generated alr eady, it is available immedi ately after the [reti] instruc- tion is executed. on the pseudo non-maskable interrupt, the non-maskable return instruction [retn] is adopted. in this case, imf flag is set to "1" only when it performs the pseu do non-maskable interrupt service routine on the interrupt acceptable status (imf=1). however, imf is set to "0" in the pseudo non-maskable interrupt service routine, it maintains its status (imf="0"). the imf is located on bit0 in eirl (address: 003ah in sfr), and can be read and written by an instruction. the imf is normally set and cl eared by [ei] and [di] instruction respectively. during reset, the imf is initial- ized to ?0?. 3.2.2 individual interrupt enable flags (ef38 to ef3) each of these flags enables and disables the acceptan ce of its maskable interrupt . setting the corresponding bit of an individual interrupt enable flag to ?1? enables acceptan ce of its interrupt, and setting the bit to ?0? dis- ables acceptance. during reset, all the i ndividual interrupt enable flags (ef38 to ef3) ar e initialized to ?0? and all maskable interrupts are not accepted until they are set to ?1?. note:in main program, before manipulating the interrupt enable flag (ef) or the interrupt latch (il), be sure to clear imf to "0" (disable interrupt by di instruction). then set imf newly again as required after operating on the ef or il (enable interrupt by ei instruction) in interrupt service routine, because the imf become s "0" automatically, clearing imf need not execute nor- mally on interrupt service routine. however, if using mult iple interrupt on interrupt service routine, manipulat- ing ef or il should be executed before setting imf="1". example :enables interrupts individually and sets imf di ; imf 0 set (eirl), .5 ; ef5 1 clr (eirl), .6 ; ef6 0 clr (eirh), .4 ; ef12 0 clr (eird), .0 ; ef24 0 : ei ; imf 1
page 22 3. interrupt control circuit 3.2 interrupt enable register (eir) TMP88PH40MG note 1: il2 cannot alone be cleard. note 2: unable to detect the under-flow of counter. note 3: the nesting counter is set "0" initially, it performs c ount-up by the interrupt acceptance and count-down by executing t he interrupt return instruction. note 4: in main program, before manipulating the interrupt enable fl ag (ef) or the interrupt latch (il), be sure to clear imf to "0" (disable interrupt by di instruction). then set imf newly again as required after operating on the ef or il (enable interrupt by ei instruction) in interrupt service routine, because the imf becomes "0" automatically, clear ing imf need not execute normally on inter- rupt service routine. however, if using multiple interrupt on interrupt service routine, mani pulating ef or il should be exe- cuted before setting imf="1". note 5: do not clear il with read-modify-w rite instructions such as bit operations. interrupt latches (initial value: ***0*0*0 *0**0000) ilh,ill (003dh, 003ch) 1514131211109876543210 - - - il12 - il10 - il8 - il6 - - il3 il2 inf ilh (003dh) ill (003ch) (initial value: *****0*0 *0*0*0*0) ild,ile (002fh, 002eh) 1514131211109876543210 -----il26-il24-il22-il20-il18-il16 ild (002fh) ile (002eh) (initial value: *0*00000) ilc (002bh) 76543210 - il38 - il36 il35 il34 il33 il32 ile (002bh) il38 to il2 interrupt latches read write r/w 0: no interrupt request 1: interrupt request 0: clears the interrupt request (note1) 1: (unable to set interrupt latch) inf interrupt nesting flag 00: out of interrupt service 01: on interrupt service of level 1 01: on interrupt service of more than level 2 01: on interrupt service of more than level 3 00: reserved 01: clear the nesting counter 10: count-down 1 step for the nesting counter (note2) 11: reserved interrupt enable registers (initial value: ***0*0*0 *0**0**0) eirh,eirl (003bh, 003ah) 1514131211109876543210 - - - ef12 - ef10 - ef8 - ef6 - - ef3 imf eirh (003bh) eirl (003ah) (initial value: *****0*0 *0*0*0*0) eird,eire (002dh, 002ch) 1514131211109876543210 -----ef26-ef24-ef22-ef20-ef18-ef16 eird (002dh) eire (002ch) (initial value: *0*00000) eire (002ah) 76543210 - ef38 - ef36 ef35 ef34 ef33 ef32 eire (002ah)
page 23 TMP88PH40MG note 1: do not set imf and the interrupt enable flag (ef38 to ef3) to ?1? at the same time. note 2: in main program, before manipulating the interrupt enable fl ag (ef) or the interrupt latch (il), be sure to clear imf to "0" (disable interrupt by di instruction). then set imf newly again as required after operating on the ef or il (enable interrupt by ei instruction) in interrupt service routine, because the imf becomes "0" automatically, clear ing imf need not execute normally on inter- rupt service routine. however, if using multiple interrupt on interrupt service routine, mani pulating ef or il should be exe- cuted before setting imf="1". ef38 to ef3 individual-interrupt enable flag (specified for each bit) 0: 1: disables the acceptance of each maskable interrupt. enables the acceptance of each maskable interrupt. r/w imf interrupt master enable flag 0: 1: disables the acceptance of all maskable interrupts enables the acceptance of all maskable interrupts
page 24 3. interrupt control circuit 3.3 interrupt sequence TMP88PH40MG 3.3 interrupt sequence an interrupt request, which raised inte rrupt latch, is held, until interrupt is accepted or interrupt latch is cleared to ?0? by resetting or an instruction. interrupt accep tance sequence requires 12 machine cycles (2.4 s @20 mhz) after the completion of the current instruction. the interrupt serv ice task terminates upon execution of an interrupt return instruction [reti] (for maskable interrupts) or [retn] (for non-maskable interrupts). figure 3-1 shows the timing chart of interrupt acceptance processing. 3.3.1 interrupt acceptance proc essing is packaged as follows. a. the interrupt master enab le flag (imf) is cleared to ?0? in or der to disable the acceptance of any fol- lowing interrupt. b. the interrupt latch (il) for the interrupt source accepted is cleared to ?0?. c. the contents of the program coun ter (pc) and the program status word, including the interrupt master enable flag (imf), are saved (pushed) on the st ack in sequence of pswh, pswl, pce, pch, pcl. meanwhile, the stack pointer (sp) is decremented by 5. d. the entry address (interrupt vect or) of the corresponding interrupt service program, loaded on the vec- tor table, is transferred to the program counter. e. read the rbs control code from the vector table, add its msb(4bit) to the register bank selecter (rbs). f. count up the interrupt nesting counter. g. the instruction stored at the entry address of the inte rrupt service program is executed. note:when the contents of psw are saved on the stack, the contents of imf are also saved. note 1: a: return address, b: entry address, c: address which reti instruction is stored note 2: on condition that interrupt is enabled, it takes 62/fc [s] at maximum (if the interrupt latch is set at the first machin e cycle on 15 cycle instruction) to start interrupt accept ance processing since its interrupt latch is set. figure 3-1 timing chart of interrupt acceptance/return in terrupt instruction example: correspondence be tween vector table address for inttbt an d the entry address of the interrupt service program interrupt request interrupt latch (il) imf execute instruction pc sp 1-machine cycle interrupt service task n-3 n-4 n-4 a n-3 n n-5 a-1 a b b+1 b+2 a+1 a+2 b+3 c+2 c+1 execute instruction execute instruction execute reti instruction interrupt acceptance a+1 a n n-2 n-1 n-2 n-1
page 25 TMP88PH40MG figure 3-2 vector table address,entry address a maskable interrupt is not accepted until the imf is set to ?1? even if th e maskable interrupt higher than the level of current servicing interrupt is requested. in order to utilize nested interrupt service, the imf is set to ?1? in the interrupt service program. in this case, acceptable interrupt sources are selectively en abled by the individual interrupt enable flags. but don?t use the read-modify-write instruction for ei rl(0003ah) on the pseudo non-maskable interrupt ser- vice task. to avoid overloaded nesting, clear the individual interrupt enable flag whose interrupt is currently serviced, before setting imf to ?1?. as for non-maskable interr upt, keep interrupt service shorten compared with length between interrupt requests; otherwise the status cannot be recovered as non-maskable interrupt would simply nested. 3.3.2 saving/restoring general-purpose registers during interrupt acceptance processing , the program counter (pc) and the program status word (psw, includes imf) are automati cally saved on the stack, but the accumulato r and others are not. these registers are saved by software if necessary. when multiple interrupt se rvices are nested, it is also necessary to avoid using the same data memory area for saving registers. the fo llowing four methods are used to save/restore the gen- eral-purpose registers. 3.3.2.1 using automatic register bank switcing by switching to non-use register bank, it can re store the general-purpose register at hige speed. usually the bank register "0" is assigned for main task and the bank register "1 to 15" are for the each interrupt service task. to make up its data memory efficiency, the common bank is assigned for non-mul- tiple intrrupt factor. it can return back to main-flow by executing the interrupt return instructions ([reti]/[retn]) from the current interrupt register bank automatically. thus, no need to restore the rbs by a program. 3.3.2.2 using register bank switching by switching to non-use register bank, it can re store the general-purpose register at hige speed. usually the bank register "0" is assigned for main task and the bank register "1 to 15" are for the each interrupt service task. example :register bank switching pintxx: (interrupt processing) ; begin of interrupt routine reti ; end of interrupt : vintxx: dp pintxx ; pintxx vector address setting db 1 ; rbs <- rbs + 1 rbs setting on pintxx 45h 23h 01h 06h fffe4h fffe5h fffe6h fffe7h vector rbs control code vector table address 12345h 12346h 12347h 12348h entry address interrupt service program
page 26 3. interrupt control circuit 3.3 interrupt sequence TMP88PH40MG 3.3.2.3 using push and pop instructions if only a specific register is saved or interrupts of the same source are nested , general-purpose registers can be saved/restored using the push/pop instructions. figure 3-3 save/store register using push and pop instructions 3.3.2.4 using data transfer instructions to save only a specific register wi thout nested interrupts, data tran sfer instructions are available. example :register bank switching pintxx: ld rbs, n ; rbs <- n begin of interrupt routine (interrupt processing) reti ; end of interrupt , restore rbs and interrupt return : vintxx: dp pintxx ; pintxx vector address setting db 0 ; rbs <- rbs + 0 rbs setting on pintxx example :save/store register us ing push and pop instructions pintxx: push wa ; save wa register (interrupt processing) pop wa ; restore wa register reti ; return example :save/store register us ing data transfer instructions pintxx: ld (gsava), a ; save a register (interrupt processing) ld a, (gsava) ; restore a register reti ; return pc l pc h psw l psw h at acceptance of an interrupt pc l pc h psw l psw h a w pc l pc h psw l psw h b-5 b-4 b-3 b-2 b-1 b address (example) sp sp sp sp at execution of push instruction at execution of pop instruction at execution of reti instruction
page 27 TMP88PH40MG figure 3-4 saving/restoring general-purpose r egisters under interrupt processing 3.3.3 interrupt return interrupt return instructions [reti]/[retn] perform as follows. interrupt requests are sampled during the final cycle of the instruction being executed. thus, the next inter- rupt can be accepted immediat ely after the interrupt retu rn instruction is executed. note: when the interrupt processing time is longer than t he interrupt request generation time, the interrupt service task is performed but not the main task. [reti] maskable interrupt return [retn] non-maskable interrupt return 1. the contents of the program counter and the program status word are restored from the stack. 2. the stack pointer is incremented 5 times. 3. the interrupt master enable flag is set to "1". 4. the interrupt nesting counter is decremented, and the interrupt nesting flag is changed. 1. the contents of the program counter and the program status word are restored from the stack. 2. the stack pointer is incremented 5 times. 3. the interrupt master enable flag is set to "1" only when a non-maskable interrupt is accepted in interrupt enable status. however, the interrupt master enable flag remains at "0" when so clear by an interrupt service program. 4. the interrupt nesting counter is decremented, and the interrupt nesting flag is changed. main task interrupt acceptance interrupt return interrupt service task saving registers restoring registers main task bank m interrupt acceptance interrupt return interrupt service task switch to bank n automatically restore to bank m automatically by [reti]/[retn] bank m bank n switch to bank n by ld, rbs and n instruction (a) saving/restoring by register bank changeover (b) saving/restoring general-purpose registers using push/pop data transfer instruction bank m
page 28 3. interrupt control circuit 3.4 software interrupt (intsw) TMP88PH40MG 3.4 software interrupt (intsw) executing the swi instruction generates a software interr upt and immediately starts interrupt processing (intsw is highest prioritized interrupt). however, if processing of a non-maskable inerrupt is already underway, executing the swi instruction will not generate a software interrupt but will result in the same operation as the nop instruc- tion. use the swi instruction only for detection of the address error or for debugging. 3.4.1 address error detection ffh is read if for some cause such as noise the cpu attempts to fetch an instruction from a non-existent memory address during single chip mode. code ffh is th e swi instruction, so a software interrupt is gener- ated and an address error is detect ed. the address error detection range can be further expanded by writing ffh to unused areas of the program memory. address trap reset is generated in case that an instruction is fetched from ram, dbr or sfr areas. 3.4.2 debugging debugging efficiency can be increased by placing the swi instruction at the software break point setting address.
page 29 TMP88PH40MG 3.5 external interrupts the TMP88PH40MG has 1 external interrupt inputs. these in puts are equipped with di gital noise reject circuits (pulse inputs of less than a certa in time are elimin ated as noise). the int0 /p10 pin can be configured as either an external inte rrupt input pin or an input/output port, and is config- ured as an input port during reset. noise reject control and int0 /p10 pin function selection are performed by the external interrupt control register (eintcr). note 1: when eintcr = "0", il3 is not set even if a falling edge is detected on the int0 pin input. note 2: when a pin with more than one function is used as an out put and a change occurs in data or input/output status, an inter - rupt request signal is generated in a pseudo manner. in this ca se, it is necessary to perform appropriate processing such as disabling the interrupt enable flag. note 1: fc: high-frequency clock [hz], *: don?t care note 2: when the external interrupt control register (eintcr) is overwritten,the noise cancel ler may not operate normally. it is rec- ommended that external interrupts are disabled using the interrupt enable register (eir). source pin sub-pin enable conditions release edge (level) digital noise reject int0 int0 p10 imf ? ef3 ? int0en=1 falling edge pulses of less than 2/fc [s] are eliminated as noise. pulses of 6/fc [s ] or more are considered to be signals. (at cgcr=0). external interrupt control register eintcr76543210 (0037h) int0en (initial value: *0** ****) int0en p10/ int0 pin configuration 0: p10 input/output port 1: int0 pin (port p10 should be set to an input mode) r/w
page 30 3. interrupt control circuit 3.5 external interrupts TMP88PH40MG
page 31 TMP88PH40MG 4. special function register the TMP88PH40MG adopts the memory mapped i/o system , and all peripheral cont rol and transfers are per- formed through the special function register (sfr) or the data buffer register (dbr). the sfr is mapped on address 0000h to 003fh, dbr is mapped on address 1f80h to 1fffh. this chapter shows the arrangement of the special functi on register (sfr) and data buffer register (dbr) for TMP88PH40MG. 4.1 sfr address read write 0000h reserved 0001h p1dr 0002h reserved 0003h p3dr 0004h p4dr 0005h reserved 0006h p6dr 0007h reserved 0008h reserved 0009h reserved 000ah reserved 000bh p1cr 000ch reserved 000dh reserved 000eh reserved 000fh tc1cr 0010h tc1dral 0011h tc1drah 0012h tc1drbl - 0013h tc1drbh - 0014h reserved 0015h reserved 0016h reserved 0017h reserved 0018h reserved 0019h reserved 001ah tc4cr 001bh tc4dr 001ch tc3dra 001dh tc3drb - 001eh tc3cr 001fh reserved 0020h reserved 0021h reserved 0022h reserved 0023h reserved 0024h reserved 0025h reserved
page 32 4. special function register 4.1 sfr TMP88PH40MG note 1: do not access reserved areas by the program. note 2: ? ; cannot be accessed. note 3: write-only registers and interrupt latches cannot use the read-modify-write instructions (bit manipulation instructions such as set, clr, etc. and logical operation instructions such as and, or, etc.). 0026h adccra 0027h adccrb 0028h adcdrl - 0029h adcdrh - 002ah eirc 002bh ilc 002ch eire 002dh eird 002eh ile 002fh ild 0030h cgcr 0031h reserved 0032h reserved 0033h reserved 0034h - wdtcr1 0035h - wdtcr2 0036h tbtcr 0037h eintcr 0038h reserved 0039h syscr2 003ah eirl 003bh eirh 003ch ill 003dh ilh 003eh pswl 003fh pswh address read write
page 33 TMP88PH40MG 4.2 dbr address pmd ch read write 1f80h ? 1f81h ? 1f82h ? 1f83h p3ode 1f84h p4ode 1f85h ? 1f86h ? 1f87h ? 1f88h ? 1f89h p3cr 1f8ah p4cr 1f8bh ? 1f8ch p6cr 1f8dh ? 1f8eh ? 1f8fh ? 1f90h ? 1f91h uartsr uartcra 1f92h ? uartcrb 1f93h rdbuf tdbuf 1f94h ? atas 1f95h ? atkey 1f96h ? siocr1 1f97h siosr siocr2 1f98h siobr0 1f99h siobr1 1f9ah siobr2 1f9bh siobr3 1f9ch siobr4 1f9dh siobr5 1f9eh siobr6 1f9fh siobr7 1fa0h for pmd ch.1 pdcra 1fa1h for pmd ch.1 pdcrb 1fa2h for pmd ch.1 pdcrc ? 1fa3h for pmd ch.1 sdreg 1fa4h for pmd ch.1 mtcra 1fa5h for pmd ch.1 mtcrb 1fa6h for pmd ch.1 mcapl ? 1fa7h for pmd ch.1 mcaph ? 1fa8h for pmd ch.1 cmp1l 1fa9h for pmd ch.1 cmp1h 1faah for pmd ch.1 cmp2l 1fabh for pmd ch.1 cmp2h 1fach for pmd ch.1 cmp3l 1fadh for pmd ch.1 cmp3h 1faeh for pmd ch.1 mdcra 1fafh for pmd ch.1 mdcrb
page 34 4. special function register 4.2 dbr TMP88PH40MG note 1: do not access reserved areas by the program. note 2: ? ; cannot be accessed. note 3: write-only registers and interrupt latches cannot use the read-modify-write instructions (bit manipulation instructions such as set, clr, etc. and logical operation instructions such as and, or, etc.). 1fb0h for pmd ch.1 emgcra 1fb1h for pmd ch.1 emgcrb 1fb2h for pmd ch.1 mdoutl 1fb3h for pmd ch.1 mdouth 1fb4h for pmd ch.1 mdcntl ? 1fb5h for pmd ch.1 mdcnth ? 1fb6h for pmd ch.1 mdprdl 1fb7h for pmd ch.1 mdprdh 1fb8h for pmd ch.1 cmpul 1fb9h for pmd ch.1 cmpuh 1fbah for pmd ch.1 cmpvl 1fbbh for pmd ch.1 cmpvh 1fbch for pmd ch.1 cmpwl 1fbdh for pmd ch.1 cmpwh 1fbeh for pmd ch.1 dtr 1fbfh for pmd ch.1 ? emgrel 1fc0h for pmd ch.1 edcra 1fc1h for pmd ch.1 edcrb 1fc2h for pmd ch.1 edsetl 1fc3h for pmd ch.1 edseth 1fc4h for pmd ch.1 eldegl 1fc5h for pmd ch.1 eldegh 1fc6h for pmd ch.1 ampl 1fc7h for pmd ch.1 amph 1fc8h for pmd ch.1 edcapl ? 1fc9h for pmd ch.1 edcaph ? 1fcah for pmd ch.1 ? wfmdr 1fcbh ? 1fcch reserved to : 1fffh reserved address pmd ch read write
page 35 TMP88PH40MG 5. input/output ports the TMP88PH40MG contains 4 input/out put ports comprised of 19 pins. all output ports contain a latch, and the output data ther efore are retained by the latch. but none of the input ports have a latch, so it is desirable that the input data be retain ed externally until it is read out, or read several times before being processed. figure 5-1 shows input/output timing. the timing at which external data is read in from input/out put ports is s1 state in the read cycle of instruction exe- cution. because this timing cannot be recognized from the out side, transient input data such as chattering needs to be dealt with in a program. the timing at which data is forwarded to input/output ports is s2 state in the write cycle of instruction execution. note: the read/write cycle positi ons vary depending on instructions. figure 5-1 example of input/output timing primary function secondary functions port p1 1-bit i/o port external interrupt input port p3 8-bit i/o port motor control input/output port p4 6-bit i/o port serial interface input/output, motor control circuit input port p6 4-bit i/o port analog input and motor control circuit output

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page 36 5. input/output ports 5.1 port p1 (only p10) TMP88PH40MG when an operation is performed for read from any input/output port except programmable input/output ports, whether the input value of the pin or the content of the output latch is read depends on the instruction executed, as shown below. 1. instructions which read the content of the output latch - xch r, (src) - set/clr/cpl (src).b - set/clr/cpl (pp).g - ld (src).b, cf - ld (pp).b, cf - xch cf, (src). b - add/addc/sub/subb/and/or/xor (src), n - add/addc/sub/subb/and/or/xor (src), (hl) instructions, the (src) side thereof - mxor (src), m 2. instructions which read the input value of the pin any instructions other than those listed above and add/addc/sub/subb/and/or/xor (src),(hl) instructions, the (hl) side thereof. 5.1 port p1 (only p10) port p1 is an 8-bit input/output port shared with external interrupt input. this port is switched between input and output modes using the p1 port input/output control register (p1cr). when reset, the p1cr register is initialized to 0, with the p1 port set for input mode. also, the output latch (p1dr) is initialized to 0 when reset. figure 5-2 port p1 p1 port input/output register p1dr (00001h) r/w 76543210 p10 int0 (initial value: **** ***0) p1cr (0000bh) 76543210 (initial value: **** ***0) p1cr p1 port input/output control (specify bitwise) 0: input mode 1: output mode r/w

page 37 TMP88PH40MG 5.2 port p3 (p37 to p30) port p3 is an 8-bit input/output port. this port is switched between input and output modes using the p3 port input/ output control register (p3cr). when rese t, the p3cr register is initialized to 0, with the p3 port set for input mode. also, the output latch (p3dr) is initialized to 0 when reset. the p3 port contains bitwise programmable open-drain control. the p3 port open-drain control register (p3ode) is used to select open-drain or tri-state mode fo r the port. when reset, the p3ode register is initialized to 0, with tri-state mode selected for the port. figure 5-3 port p3 note 1: even when open-drain mode is selected, the protecti ve diode remains connected. therefore, do not apply voltages exceeding v dd . note 2: if read-modify-write instruction is executed while the r egister is selecting open-drain mode, output latch data are read out. at the other instruction is executed, external pin states are read out. note 3: for pmd circuit output, set the p3dr output latch to 1. note 4: when using p3 port as an input/ output port, disable the emg1 circuit. p3 port input/output registers p3dr (00003h) r/w 76543210 p37 cl1 p36 emg1 p35 u1 p34 v1 p33 w1 p32 x1 p31 y1 p30 z1 (initial value: 0000 0000) p3cr (01f89h) 76543210 (initial value: 0000 0000) p3cr p3 port input/output control (specify bitwise) 0: input mode 1: output mode r/w p3ode (01f83h) 76543210 (initial value: 0000 0000) p3ode p3 port open-drain control (specify bitwise) 0: tri-state 1: open-drain r/w

page 38 5. input/output ports 5.1 port p1 (only p10) TMP88PH40MG 5.3 port p4 (p45 to p40) port p4 is an 6-bit input/output port shared with serial interface input/output. this por t is switched between input and output modes using the p4 port input/output control regi ster (p4cr). when reset, the p4cr register is initialized to 0, with the p4 port set for input mode. also, the output latch (p4dr) is initialized to 0 when reset. the p4 port contains bitwise programmable open-drain cont rol. the p4 port open-drain control register (p4ode) is used to select open-drain or tri-state mode for the port. when reset, the p4ode register is initialized to 0, with tri- state mode selected for the port. figure 5-4 port p4 note 1: even when open-drain mode is selected, the protecti ve diode remains connected. therefore, do not apply voltages exceeding v dd . note 2: if read-modify-write instruction is executed while the r egister is selecting open-drain mode, output latch data are read out. at the other instruction is executed, external pin states are read out. note 3: *: don?t care p4 port input/output registers p4dr (00004h) r/w 76543210 p45 so txd1 p44 si rxd1 p43 sck p42 pdu1 p41 pdv1 p40 pdw1 (initial value: **00 0000) p4cr (01f8ah) 76543210 (initial value: **00 0000) p4cr p4 port input/output control (specify bitwise) 0: input mode 1: output mode r/w p4ode (01f84h) 76543210 (initial value: **00 0000) p4ode p4 port open-drain control (specify bitwise) 0: tri-state 1: open-drain r/w

page 39 TMP88PH40MG 5.4 port p6 (p63 to p60) port p6 is an 4-bit input/output port shared with ad co nverter analog input. this port is switched between input and output modes using the p6 port input/output control register (p6cr), p6 port output latch (p6dr), and adc- cra. when reset, the p6cr register and the p6dr output latch are initialized to 0 while adc- cra is set to 1, so that p63 to p60 have their inpu ts fixed low (= 0). when using the p6 port as an input port, set the corresponding bits for input mode (p6cr = 0, p6dr = 1). the reason why the output latch = 1 is because it is necessary to prevent curren t from flowing into the shared data in put circuit. when us ing the port as an output port, set the p6cr register's corresponding bits to 1. when using the port for analog input, set the corre- sponding bits for analog input (p6cr = 0, p6dr = 0). then set adccra = 0, and ad conversion will start. the ports used for analog input must have their output latches set to 0 beforehand. the actual input channels for ad conversion are selected using adccra. although the bits of p6 port not used for analog input can be used as input/output ports, do not execute output instructions on these ports during ad conversion. this is necessary to ma intain the accuracy of ad conversion. also, do not apply rapidly changing signals to ports adjacent to analog input during ad conversion. if an input instruction is executed while the p6dr output latc h is cleared to 0, data ?0? is read in from said bits. figure 5-5 port p6 note 1: the pins used for analog input cannot be set for output mode (p6cr = 1) because they become shorted with external signals. note 2: when a read instruction is executed on bits of this por t which are set for analog input mode, data "0" is read in. note 3: for dbout output, set the p6dr (p63) output latch to 1. note 4: *: don?t care note 5: when using this port in input mode (including analog input), do not use bit manipulating or ot her read-modify-write inst ruc- tions. when a read instruction is executed on the bits of this port that are set for input, the contents of the pins are read i n, so that if a read-modify-write instruction is executed, t heir output latches may be rewritten, making the pins unable to p6 port input/output registers p6dr (00006h) r/w 76543210 p63 ain3 dbout p62 ain2 p61 ain1 p60 ain0 (initial value: **** 0000) p6cr (01f8ch) 76543210 (initial value: **** 0000) p6cr p6 port input/output control (specify bitwise) ainds = 1 (when not using ad) ainds = 0 (when using ad) r/w p6dr = ?0? p6dr = ?1? p6dr = ?0? p6dr = ?1? 0 inputs fixed to 0 input mode analog input mode (note2) input mode 1 output mode output mode

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page 40 5. input/output ports 5.1 port p1 (only p10) TMP88PH40MG accept input. (a read-modify-write instruct ion first reads data from all of the eight bits and after modifying them (bit manip- ulation), writes data for all of the eight bits to the output latches.)
page 41 TMP88PH40MG 6. watchdog timer (wdt) the watchdog timer is a fail-safe system to detect rapidl y the cpu malfunctions such as endless loops due to spu- rious noises or the deadlock conditions, and return the cpu to a sy stem recovery routine. the watchdog timer signal for detecting malfunctions can be programmed only once as ?r eset request? or ?pseudo nonmaskable interrupt request?. upon the reset releas e, this signal is initia lized to ?reset request?. when the watchdog timer is not used to detect malfunctions, it can be used as the timer to provide a periodic inter- rupt. note: care must be taken in system des ign since the watchdog timer functions are not be operated completely due to effect of disturbing noise. 6.1 watchdog timer configuration figure 6-1 watchdog timer configuration 0034 h overflow wdt output internal reset binary counters wdtout writing clear code writing disable code wdten wdtt 2 0035 h watchdog timer control registers wdtcr1 wdtcr2 intwdt interrupt request interrupt request reset request reset release clock clear 1 2 controller q sr s r q selector fc/2 23 ,fc/2 24 fc/2 21 ,fc/2 22 fc/2 19 ,fc/2 20 fc/2 17 ,fc/2 18
page 42 6. watchdog timer (wdt) 6.2 watchdog timer control TMP88PH40MG 6.2 watchdog timer control the watchdog timer is controlled by the watchdog timer control registers (wdtcr1 and wdtcr2). the watch- dog timer is automatically enabled after the reset release. 6.2.1 malfunction detection me thods using the watchdog timer the cpu malfunction is detected, as shown below. 1. set the detection time, select the output, and clear the binary counter. 2. clear the binary counter repeatedly within the specified detection time. if the cpu malfunctions such as en dless loops or the deadlock condition s occur for some reason, the watch- dog timer output is activated by the binary-counter overflow unless the binary counters are cleared. when wdtcr1 is set to ?1? at this time, the reset request is generated and then internal hardware is initialized. when wdtcr1 is set to ?0?, a watchdog timer interrupt (intwdt) is generated. the watchdog timer temporarily stops counting in the idle mode, and automatically restarts (continues counting) when the idle mode is inactivated. note:the watchdog timer consists of an internal divider and a two-stage binary counter. when the clear code 4eh is written, only the binary counter is cleared, but not the internal divider . the minimum binary-counter overflow time, that depends on the timing at which the clear code (4eh) is written to the wdtcr2 register, may be 3/ 4 of the time set in wdtcr1. therefore, writ e the clear code using a cycle shorter than 3/4 of the time set to wdtcr1. example :setting the watchdog timer detection time to 2 21 /fc [s], and resetting the cpu malfunction detection ld (wdtcr2), 4eh : clears the binary counters. ld (wdtcr1), 00001101b : wdtt 10, wdtout 1 ld (wdtcr2), 4eh : clears the binary counters (always clears immediately before and after changing wdtt). within 3/4 of wdt detection time : : ld (wdtcr2), 4eh : clears the binary counters. within 3/4 of wdt detection time : : ld (wdtcr2), 4eh : clears the binary counters.
page 43 TMP88PH40MG note 1: after clearing wdtcr1 to ?0?, the program cannot set it to ?1?. note 2: fc: high-frequency clock [hz], *: don?t care note 3: wdtcr1 is a write-only register and must not be used with any of read-modify-write instructions. if wdtcr1 is read, a unknown data is read. note 4: to clear wdtcr1, set the register in acco rdance with the procedures shown in ?6.2.3 watchdog timer dis- able?. note 5: if the watchdog timer is disabled during watchdog timer in terrupt processing, the watchdog timer interrupt will never be cleared. therefore, clear the watchdog timer ( set the clear co de (4eh) to wdtcr2 ) before disabling it, or disable the watchdog timer a sufficient time before it overflows. note 6: the watchdog timer consists of an internal divider and a two-stage binary counter. when clear code (4eh) is written, onl y the binary counter is cleared, not the internal divider. depending on the timing at which clear code (4eh) is written on the wdtcr2 register, the overflow time of the binary counter may be at minimum 3/4 of the time set in wdtcr1. thus, write the clear c ode using a shorter cycle than 3/4 of the time set in wdtcr1. note 1: the disable code is valid only when wdtcr1 = 0. note 2: *: don?t care note 3: the binary counter of the watchdog timer must not be cleared by the interrupt task. note 4: write the clear code (4eh) using a cycle shorter than 3/4 of the time set in wdtcr1. note 5: wdtcr2 is a write-only register and must not be used with any of read-modify-write instructions. if wdtcr2 is read, a unknown data is read. 6.2.2 watchdog timer enable setting wdtcr1 to ?1? enables the watc hdog timer. since wdtcr1 is initialized to ?1? during reset, the watchdog timer is enabled automatically after the reset release. watchdog timer control register 1 wdtcr1 (0034h) 76543210 wdten wdtt wdtout (initial value: **** 1001) wdten watchdog timer enable/disable 0: disable (writing the disable code to wdtcr2 is required.) 1: enable write only wdtt watchdog timer detection time [s] normal mode write only dv1ck = 0 dv1ck = 1 00 2 25 /fc 2 26 /fc 01 2 23 /fc 2 24 /fc 10 2 21 fc 2 22 fc 11 2 19 /fc 2 20 /fc wdtout watchdog timer output select 0: interrupt request 1: reset request write only watchdog timer control register 2 wdtcr2 (0035h) 76543210 (initial value: **** ****) wdtcr2 write watchdog timer control code 4eh: clear the watchdog timer binary counter (clear code) b1h: disable the watchdog timer (disable code) others: invalid write only
page 44 6. watchdog timer (wdt) 6.2 watchdog timer control TMP88PH40MG 6.2.3 watchdog timer disable to disable the watchdog timer, set the register in accordance with the fo llowing procedures . setting the reg- ister in other procedures causes a malfunction of the microcontroller. 1. set the interrupt master flag (imf) to ?0?. 2. set wdtcr2 to the clear code (4eh). 3. set wdtcr1 to ?0?. 4. set wdtcr2 to the disable code (b1h). note:while the watchdog timer is disabled, the binary counters of the watchdog timer are cleared. note: if the watchdog timer is disabled during watchdog timer inte rrupt processing, the watchdog ti mer interrupt will never be cleared. therefore, clear the watchdog timer ( set the clear c ode (4eh) to wdtcr2 ) before disabling it, or disable the watchdog timer a sufficient time before it overflows. 6.2.4 watchdog time r interrupt (intwdt) when wdtcr1 is cleared to ?0?, a watchdog timer interrupt request (intwdt) is generated by the binary-counter overflow. a watchdog timer interrupt is the non-maskable interr upt which can be accepted regardless of the interrupt master flag (imf). when a watchdog timer interrupt is generated while the other interrupt including a watchdog timer interrupt is already accepted, the new watchdog timer interrupt is processed immediately and the previous interrupt is held pending. therefore, if watchdog timer interrupts are generated continuously without execution of the retn instruction, too many levels of nesting may cause a malfunction of the microcontroller. to generate a watchdog timer interrupt, set the stack pointer before setting wdtcr1. example :disabling the watchdog timer di : imf 0 ld (wdtcr2), 04eh : clears the binary coutner ldw (wdtcr1), 0b101h : wdten 0, wdtcr2 disable code ei : imf 1 table 6-1 watchdog timer detection time (example: fc = 20 mhz) wdtt watchdog timer detection time[s] normal mode dv1ck = 0 dv1ck = 1 00 1.678 3.355 01 419.430 m 838.861 m 10 104.858 m 209.715 m 11 26.214 m 52.429 m
page 45 TMP88PH40MG 6.2.5 watchdog timer reset when a binary-counter overflow occurs while wdt cr1 is set to ?1?, a watchdog timer reset request is generated. when a watchdog timer reset request is generated, the internal hardware is reset. the reset time is maximum 24/fc [s] ( max. 1.2 s @ fc = 20 mhz). figure 6-2 watchdog ti mer interrupt and reset example :setting watchdog timer interrupt ld sp, 02bfh : sets the stack pointer ld (wdtcr1), 00001000b : wdtout 0 clock binary counter overflow intwdt interrupt request (wdtcr1= "0") 2 17 /fc 2 19 /fc [s] (wdtt=11b) write 4e h to wdtcr2 1 2 30 1 2 3 0 internal reset (wdtcr1= "1") a reset occurs
page 46 6. watchdog timer (wdt) 6.2 watchdog timer control TMP88PH40MG
page 47 TMP88PH40MG 7. time base timer (tbt) 7.1 time base timer the time base timer generates time base for key scanning, dynamic displaying, etc. it also provides a time base timer interrupt (inttbt). an inttbt ( time base timer interrupt ) is generated on the first falling edge of source clock ( the divider out- put of the timing generator which is selected by tbtck. ) after time base timer has been enabled. the divider is not cleared by the program; therefore, onl y the first interrupt may be generated ahead of the set interrupt period ( figure 7-2 ). the interrupt frequency (tbtck) must be selected with the time base timer disabled (tbten="0"). (the inter- rupt frequency must not be changed with the disble from the enable state.) both frequency selection and enabling can be performed simultaneously. figure 7-1 time base timer configuration figure 7-2 time base timer interrupt example :set the time base timer frequency to fc/2 16 [hz] and enable an inttbt interrupt. ld (tbtcr) , 00000010b ; tbtck 010 (freq. set) ld (tbtcr) , 00001010b ; tbten 1 (tbt enable) di set (eirl) . 6 ei fc/2 23 ,fc/2 24 fc/2 21 ,fc/2 22 fc/2 16 ,fc/2 17 fc/2 14 ,fc/2 15 fc/2 13 ,fc/2 14 fc/2 12 ,fc/2 13 fc/2 11 ,fc/2 12 fc/2 9 ,fc/2 10 tbtcr tbten tbtck 3 mpx source clock falling edge detector time base timer control register inttbt interrupt request source clock enable tbt interrupt period tbtcr inttbt interrupt request
page 48 7. time base timer (tbt) 7.1 time base timer TMP88PH40MG time base timer is controled by time base timer control register (tbtcr). note 1: fc; high-frequency clock [hz], *; don't care note 2: always set "0" in bit4 to bit7 on tbtcr register. time base timer control register 7 6543210 tbtcr (00036h) 0 0 0 tbten tbtck (initial value: 0000 0000) tbten time base timer enable / disable 0: disable 1: enable tbtck time base timer interrupt frequency select : [hz] normal, idle mode r/w dv1ck=0 dv1ck=1 000 fc/2 23 fc/2 24 001 fc/2 21 fc/2 22 010 fc/2 16 fc/2 17 011 fc/2 14 fc/2 15 100 fc/2 13 fc/2 14 101 fc/2 12 fc/2 13 110 fc/2 11 fc/2 12 111 fc/2 9 fc/2 10 table 7-1 time base timer interrupt frequency ( example : fc = 20.0 mhz ) tbtck time base timer interrupt frequency [hz] normal, idle mode dv1ck = 0 dv1ck = 1 000 2.38 1.20 001 9.53 4.78 010 305.18 153.50 011 1220.70 610.35 100 2441.40 1220.70 101 4882.83 2441.40 110 9765.63 4882.83 111 39063.00 19531.25
page 49 TMP88PH40MG 8. 16-bit timercounter 1 (tc1) 8.1 configuration figure 8-1 timercounter 1 (tc1) 8.2 timercounter control the timercounter 1 is controlled by the timercounter 1 control register (tc1cr) and two 16-bit timer registers (tc1dra and tc1drb). timer register 1514131211109876543210 tc1dra (0011h, 0010h) tc1drah (0011h) tc1dral (0010h) (initial value: 1111 1111 1111 1111) read/write tc1drb (0013h, 0012h) tc1drbh (0013h) tc1drbl (0012h) (initial value: 1111 1111 1111 1111) read only timercounter 1 control register tc1cr (000fh) 76543210 0 acap1 tc1s tc1ck tc1m read/write (initial value: 0000 0000) cmp start 16-bit timer register a, b capture source clock 16-bit up-counter clear tc1drb tc1dra tc1cr tc1 control register match inttc1 interrupt acap1 tc1ck 2 y a b c s tc1s 2 set clear command start decoder q fc/2 11 , fc/2 12 fc/2 7 , fc/2 8 fc/2 3 , fc/2 4
page 50 8. 16-bit timercounter 1 (tc1) 8.2 timercounter control TMP88PH40MG note 1: fc: high-frequency clock [hz] note 2: the timer register consists of two shift registers. a va lue set in the timer register becomes valid at the rising edge o f the first source clock pulse that occurs after the upper byte (t c1drah and tc1drbh) is written. therefore, write the lower byte and the upper byte in this order (it is recommended to write the register with a 16-bit acce ss instruction). writing only the lower byte (tc1dral) does not enable the setting of the timer register. note 3: to set the mode and source clock, write to tc1cr during tc1cr=00. note 4: to set the timer registers, the following relationship must be satisfied. tc1dra > 1 note 5: set tc1cr register bit7 to ?0?. note 6: use the auto-capture function in the operative condition of tc1. a captured value may not be fixed if it's read after th e execution of the timer stop or auto-capture disable. read the capture value in a capture enabled condition. note 7: since the up-counter value is captured into tc1drb by the source clock of up-counter after setting tc1cr to "1". therefore, to read the captured value, wait at least one cycle of the internal source clock before reading tc1drb for the first time. acap1 auto capture control 0:auto-capture disable 1:auto-capture enable r/w tc1s tc1 start control 00: stop and counter clear 01: command start 10: reserved 11: reserved r/w tc1ck tc1 source clock select [hz] normal, idle mode r/w dv1ck = 0 dv1ck = 1 00 fc/2 11 fc/2 12 01 fc/2 7 fc/2 8 10 fc/2 3 fc/2 4 11 reserved tc1m tc1 operating mode select 00: timer mode 01: reserved 10: reserved 11: reserved r/w
page 51 TMP88PH40MG 8.3 function 8.3.1 timer mode in the timer mode, the up-counter counts up using the in ternal clock. when a match between the up-counter and the timer register 1a (tc1dra) va lue is detected, an inttc1 interrupt is generated and the up-counter is cleared. after being cleared, the up-c ounter restarts counting. setting tc 1cr to ?1? captures the up- counter value into the timer register 1b (tc1drb) wi th the auto-capture functi on. use the auto-capture function in the operative condition of tc1. a captured valu e may not be fixed if it's read after the execution of the timer stop or auto-capture disabl e. read the capture value in a cap ture enabled condition. since the up- counter value is captured into tc1drb by the source clock of up-counter after setting tc1cr to "1". therefore, to read the captured va lue, wait at least one cy cle of the internal sour ce clock before reading tc1drb for the first time. table 8-1 source clock for timercounter 1 (example: fc = 20 mhz) tc1ck normal, idle mode dv1ck = 0 dv1ck = 1 resolution [ s] maximum time setting [s] resolution [ s] maximum time setting [s] 00 102.4 6.7108 204.8 13.4216 01 6.4 0.4194 12.8 0.8388 10 0.5 26.214 m 0.8 52.428 m example 1 :setting the timer mode with source clock fc/2 11 [hz] and generating an interrupt 1 second later (fc = 20 mhz, cgcr = ?0?) ldw (tc1dra), 2625h ; sets the timer register (1 s 2 11 /fc = 2625h) di ; imf = ?0? set (eird). 2 ; enables inttc1 ei ; imf = ?1? ld (tc1cr), 00000000b ; selects the source clock and mode ld (tc1cr), 00010000b ; starts tc1 example 2 :auto-capture ld (tc1cr), 01010000b ; acap1 1 ; wait at least one cycle of the internal source clock ld wa, (tc1drb) ; reads the capture value
page 52 8. 16-bit timercounter 1 (tc1) 8.3 function TMP88PH40MG figure 8-2 timer mode timing chart match detect acap1 tc1drb tc1dra inttc1 interruput request source clock counter source clock counter ? (a) timer mode (b) auto-capture ? 7 6 345 0 timer start 12 3 2 1 4 0 counter clear capture n + 1 n n n m + 2 m + 1 m m capture m + 2 m + 1 n + 1 n m ? 1 m ? 1 m ? 2 n ? 1 n ? 1 n ? 1
page 53 TMP88PH40MG 9. 8-bit timercounter 3 (tc3) 9.1 configuration note: function input may not operate depending on i/o port setti ng. for more details, see the chapter "i/o port". figure 9-1 time rcounter 3 (tc3) tc3ck tc3s fc/2 13 , fc/2 14 fc/2 12 , fc/2 13 fc/2 11 , fc/2 12 fc/2 10 , fc/2 11 fc/2 9 , fc/2 3 source clock clear tc3s inttc3 interrupt tc3 control register 8-bit timer register a b c d e f g s tc3cr tc3drb tc3dra capture acap match detect y 8-bit up-counter 10 fc/2 8 , fc/2 9 fc/2 7 , fc/2 8 cmp
page 54 9. 8-bit timercounter 3 (tc3) 9.1 configuration TMP88PH40MG 9.2 timercounter control the timercounter 3 is controlled by the timercounter 3 control register (tc3cr) and two 8-bit timer registers (tc3dra and tc3drb). note 1: fc: high-frequency clock [hz], * : don?t care note 2: set the source clock when timercounter stops (tc3cr = 0). note 3: to set the timer registers, the following relationship must be satisfied. tc3dra > 1 note 4: when the read instruction is executed to tc3cr, the bit 5 and 7 are read as a don?t care. note 5: do not program tc3dra when the timer is running (tc3cr = 1). timer register and control register tc3dra (001ch) 76543210 read/write (initial value: 1111 1111) tc3drb (001dh) read only (initial value: 1111 1111) tc3cr (001eh) 76543210 acap tc3s tc3ck tc3m (initial value: *0*0 0000) acap auto capture control 0: ? 1: auto capture r/w tc3s tc3 start control 0: stop and counter clear 1: start r/w tc3ck tc3 source clock select [hz] normal, idle mode r/w dv1ck=0 dv1ck=1 000 fc/2 13 fc/2 14 001 fc/2 12 fc/2 13 010 fc/2 11 fc/2 12 011 fc/2 10 fc/2 11 100 fc/2 9 fc/2 10 101 fc/2 8 fc/2 9 110 fc/2 7 fc/2 8 111 reserved tc3m tc3 operating mode select 0: timer mode 1: reserved r/w
page 55 TMP88PH40MG 9.3 function 9.3.1 timer mode in the timer mode, the up-counter counts up using the internal clock. when a match between the up-counter and the timer register 3a (tc3dra) value is detected, an inttc3 interrupt is generated and the up-counter is cleared. after being cleared , the up-counter restarts counting. setting tc3cr to 1 captures the up- counter value into the timer register 3b (tc3drb) with the auto-capture function. the count value during timer operation can be checked by execu ting the read instruction to tc3drb. note:00h which is stored in the up-counter immediately after detection of a match is not captured into tc3drb. (figure 9-2) figure 9-2 auto -capture function table 9-1 source clock for timercounter 3 (example: fc = 20 mhz) tc3ck normal, idle mode dv1ck = 0dv1ck = 1 resolution [ s] maximum time setting [ms] resolution [ s] maximum time setting [ms] 000 409.6 104.45 819.2 208.90 001 204.8 52.22 409.6 104.45 010 102.4 26.11 204.8 52.22 011 51.2 13.06 102.4 26.11 100 25.6 6.53 51.2 13.06 101 12.8 3.06 25.6 6.53 110 6.4 1.63 12.8 3.06 tc3drb note: in the case that tc3drb is c8h clock up-counter match detect c7 c8 tc3dra c8 00 01 c7 c8 c6 c6 01
page 56 9. 8-bit timercounter 3 (tc3) 9.1 configuration TMP88PH40MG figure 9-3 timer mode timing chart match detect tc3cr tc3drb tc3dra inttc3 interrupt source clock counter source clock counter (a) timer mode (b) auto capture ? ? 7 6 3 4 5 0 n timer start 1 2 3 2 1 4 0 n counter clear capture n + 1 n m + 2 m + 1 m m capture m + 2 m + 1 n + 1 n
page 57 TMP88PH40MG 10. 8-bit timercounter 4 (tc4) 10.1 configuration figure 10-1 timercounter 4 (tc4) a by c d s 8-bit up-counter cmp match detect source clock 8-bit timer register inttc4 interrupt fc/2 11 , fc/2 12 fc/2 7 , fc/2 8 fc/2 5 , fc/2 6 fc/2 3 , fc/2 4 tc4cr tc4m tc4s tc4ck tc4dr tc4s clear tc4 control register
page 58 10. 8-bit timercounter 4 (tc4) 10.1 configuration TMP88PH40MG 10.2 timercounter control the timercounter 4 is controlled by the timercounter 4 c ontrol register (tc4cr) and timer registers 4 (tc4dr). note 1: fc: high-frequency clock [hz], * : don?t care note 2: to set the timer registers, the following relationship must be satisfied. 1 tc4dr 255 note 3: to start timer operation (tc4cr = 0 1) or disable timer operation (tc4cr = 1 0), do not change the tc4cr setting. during timer operation (tc4cr = 1 1), do not change it, either. if the setting is programmed during timer operation, counting is not performed correctly. note 4: the bit 6 and 7 of tc4cr are read as a don?t care when these bits are read. note 5: do not change the tc4dr setting when the timer is running. timer register and control register tc4dr (001bh) 76543210 read/write (initial value: 1111 1111) tc4cr (001ah) 76543210 tc4s tc4ck tc4m read/write (initial value: **00 0000) tc4s tc4 start control 0: stop and counter clear 1: start r/w tc4ck tc4 source clock select [hz] normal, idle mode r/w dv1ck = 0dv1ck = 1 000 fc/2 11 fc/2 12 001 fc/2 7 fc/2 8 010 fc/2 5 fc/2 6 011 fc/2 3 fc/2 4 100 reserved reserved 101 reserved reserved 110 reserved reserved 111 reserved tc4m tc4 operating mode select 00: timer mode 01: reserved 10: reserved 11: reserved r/w
page 59 TMP88PH40MG 10.3 function 10.3.1 timer mode in the timer mode, the up-counter counts up using the internal clock. when a match between the up-counter and the tc4dr value is detected, an inttc4 interrupt is generated and the up-counter is cleared. after being cleared, the up-counter restarts counting. table 10-1 internal source clock for timercounter 4 (example: fc = 20 mhz) tc4ck normal, idle mode dv1ck = 0 dv1ck = 1 resolution [ s] maximum time setting [ms] resolution [ s] maximum time setting [ms] 000 102.4 26.11 204.8 52.22 001 6.4 1.63 12.8 3.28 010 1.6 0.41 3.2 0.82 011 0.4 0.10 0.8 0.20
page 60 10. 8-bit timercounter 4 (tc4) 10.1 configuration TMP88PH40MG
page 61 TMP88PH40MG 11. motor control circuit (pmd: programmable motor driver) the TMP88PH40MG contains one channel of motor contro l circuits used for sinusoidal waveform output. this motor control circuit can control brushless dc motors or ac motors with or without sensors. with its primary func- tions like those listed below incorporated in hardware, it helps to accomplish sine wave mo tor control easily, with the software load significantly reduced. 1. rotor position detect function ? can detect the rotor position, with or without sensors ? can be set to determine the rotor position when detection matched a number of times, to prevent erro- neous detection ? can set a position detection inhibit period immediately after pwm-on 2. independent timer and timer capture functions for motor control ? contains one-channel magnitude comparison time r and two-channel coinci dence comparison timers that operate synchronously for position detection 3. pwm waveform generating function ? generates 12-bit pwm with 100 ns resolution ? can set a frequency of pwm interrupt occurrence ? can set the dead time at pwm-on 4. protective function ? provides overload protective function based on protection signal input 5. emergency stop function in case of failure ? can be made to stop in an emergency by emg input or timer overflow interrupt ? not easily cleared by software runaway 6. auto commutation/auto position detection start function ? comprised of dual-buffers, can activate auto commutation synchronously with position detection or timer ? can set a position detection period using the timer f unction and start auto position detection at the set time 7. electrical angle timer function ? can count 360 degrees of electrical angle with a set period in the range of 0 to 383 ? can output the counted el ectrical angle to the wave form arithmetic circuit 8. waveform arithmetic circuit ? calculate the output duty cycle fro m the sine wave data and voltage data which are read from the ram based on the elect rical angle timer ? output the calculation result to the waveform synthesis circuit
page 62 11. motor contro l circuit (pmd: programmable motor driver) TMP88PH40MG 11.1 outline of motor control the following explains the method for controlling a brushless dc motor with sine wave drive. in a brushless dc motor, the rotor windings to which to apply electric current are determined from the rotor?s magnetic pole position, and the current-applied windings are ch anged as the rotor turns. the rotor?s magnetic pole position is determined using a sensor such as a hall ic or by detecting polarity ch ange (zero-cross) points of the induced voltage that devel- ops in the motor windings (sensorless control). for the sens orless case, the induced voltage is detected by applying electric current to two phases and not applying electric current to the remaining other phase. in this two-phase cur- rent on case, there are six current application patterns as shown in table 11-1, which are changed synchronously with the phases of the rotor. in this two-phase current on case, the current on time in each phase is 120 degrees relative to 180 degrees of the induced voltage. note: one of the upper or lower transistors is pwm controlled. for brushless dc motors, the number of revolutions is controlled by an applied voltage, and the voltage applica- tion is controlled by pwm. at this time, the current on wi ndings need to be changed in synchronism with the phases of the voltage induced by revolutions. control timing in cases where the current on wi ndings are changed by means of sensorless control is illustrated in figure 11-4. for th ree-phase motors, zero-crossing occurs six times during one cycle of the induced voltage (electrical angle 360 degrees), so that the elect rical angle from on e zero-cross point to the next is 60 degrees. assuming that this period comprises one mode, the rotor position can be divided into six modes by zero-cross points. the six current application pa tterns shown above correspond one for one to these six modes. the timing at which the curr ent application patterns are changed (c ommutation) is out of phase by 30 degrees of electrical angle, wi th respect to the position det ection by an induced voltage. mode time is obtained by detecting a zero-cross point at some timing and finding an elapsed time from the preced- ing zero-cross point. because mode time co rresponds to 60 degrees of electrical angle, the following applies for the case illustrated in figure 11-4. 1. current on windings changeover (commutation) timing 30 degrees of electrical angle = mode time/2 2. position detection start timing 45 degrees of electrical angle = mode time 3/4 3. failure determination timing 120 degrees of electrical angle = mode time 2 timings are calculated in this way. the position detection start timing in 2 is needed to prevent erroneous detection of the induced voltage for reasons that even after current applicat ion is turned off, the current continues flowing due to the motor reactance. control is exercised by calculating the above timings successively for each of the zero-cross points detected six times during 360 degrees of electrical angle and activating commutation, position detection start, and other opera- tions according to that timing. in this way, operations can be synchronized to the phases of the induced voltage of the motor. the timing needed for motor control as in this example can be set freely as desired by using the internal timers of the microcontroller?s pmd unit. also, sine wave control requires controlling the pwm duty cycle for each pulse. co ntrol of pwm duty cycles is accomplished by counting degrees of electrical angle and cal culating the sine wave data and voltage data at the counted degree of electrical angle. table 11-1 current application patterns current application pattern upper transistor lower transistor current on winding uvwxyz mode 0 on off off off on off u v mode 1 on off off off off on u w mode 2 off on off off off on v w mode 3 off on off on off off v u mode 4 off off on on off off w u mode 5 off off on off on off w v
page 63 TMP88PH40MG figure 11-1 conc eptual diagram of dc motor control figure 11-2 example of sensorle ss dc motor control timing chart
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page 64 11. motor contro l circuit (pmd: programmable motor driver) TMP88PH40MG 11.2 configuration of t he motor control circuit the motor control circuit consists of various units. these include a position de tection unit to det ect the zero-cross points of the induced voltage or position sensor signal, a timer unit to generate events at three instances of electrical angle timing, and a three-phase pwm output unit to produ ce three-phase output pwm wave forms. also included are an electrical angle timer unit to count degrees of electrical angle and a waveform arithmetic unit to calculate sinuso- idal waveform output duty cycles. the input/output units ar e configured as shown in the diagram below. when using ports for the pmd function, set the port input/output control register (p3cri) to 0 for the input ports, and for the out- put ports, set the data output latch (p3i) to 1 and then the port input/output control register to 1. other input/output ports can be set in the same way for use of the pmd function. figure 11-3 block diagram of the motor control circuit note 1: always use the ldw instruction to set data in the 9, 12 and 16-bit data registers. note 2: the emg circuit initially is enabl ed. for pmd output, fix the emg input port (p36) "h" high level or disable the emg circuit before using for pmd output. note 3: the emg circuit initially is enabled. when using port p3 as input/output io ports, disable emg. note 4: when going to stop mode, be sure to turn all of the pmd functions off before entering stop mode.

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page 65 TMP88PH40MG 11.3 position detection unit the position detection unit identifies the motor's rotor position from input patterns on the position signal input port. applied to this position signal input port is the volta ge status of the motor windin gs for the case of sensorless dc motors or a hall element signal fo r the case of dc motors with sensors included. the expect ed patterns corre- sponding to specific rotor positions are set in the pmd ou tput register (mdout) beforehand, and when the input position signal and the expected value ma tch as the rotation, a position detec tion interrupt (intpdc) is generated. also, unmatch detection mode is used to detect the direction of motor rotation, where when the stat us of the position detection input port changes from the status in which it was at start of sampling, a position detection interrupt is gen- erated. for three-phase brushless dc motors, there are six patte rns of position signals, one for each mode, as summarized in table 11-2 from the timing chart in figure 11-2. once a predicted position signal pattern is set in the mdout reg- ister, a position detection interrupt is generated the moment the position signal input port goes to mode indicated by this expected value. the position sign als at each phase in the diagram are in ternal signals which cannot be observed from the outside. table 11-2 position signal input patterns position detection mode u phase (pdu) v phase (pdv) w phase (pdw) mode 0 h l h mode 1 h l l mode 2 h h l mode 3 l h l mode 4 l h h mode 5 l l h
page 66 11. motor contro l circuit (pmd: programmable motor driver) TMP88PH40MG 11.3.1 configuration of the position detection unit figure 11-4 configuration of the position detection circuit ? the position detection unit is controlled by the position detection control register (pdcra, pdcrb). after the position de tection function is enab led, the unit starts sa mpling the position detec- tion port with timer 2 or in software. for the case of ordinary mode, when the status of the position detection input port matches the expected value of the pmd output register, the unit generates a posi- tion detection interrupt and finishes sampling, waiting for start of the next sampling. ? when unmatch detection mode is selected for position detection, the unit stores the sampled status of the position detection port in memory at the time it started sampling. when the port input status changes from the status in which it was at st art of sampling, an interrupt is generated. ? in unmatch detection mode, the port status at start of sampling can be read (pdcrc). ? when starting and stopping position detection synchronously with the timer, position detection is started by timer 2 and position detection is stopped by timer 3. ? sampling mode can be selected from three modes available: mode where sampling is performed only while pwm is on, mode where sens ors such as hall elements are sa mpled regularly, and mode where sampling is performed while the lower side is conducting current (when performing sampling only while pwm is on, duty must be set for all three phas es in common). ? when sampling mode is selected for detecting pos ition while the lower phases are conducting current, sampling is performed for a period from when the set sampling delay time has elapsed after the lower side started conducting current till when the current appli cation is turned off. sampling is performed independently at each phase, and the sampling result is retained while sampling is idle. if while sam- pling at some phase is idle, the input and the expected value at other phase being sampled match, posi- tion is detected and an interrupt is generated.

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page 67 TMP88PH40MG ? a sampling delay is provided for use in modes where sampling is made while pwm is on or the lower phases are conducting current. it he lps to prevent erroneous detection due to noise that occurs immedi- ately after the transistor turns on, by starting sampling a set time after the pwm signal turned on. ? when detecting position while pwm is on or the lowe r phases are conducting current, a method can be selected whether to recount occurrences of matche d position detection after being compared for each pwm signal on (logical sum of three-phase pwm signals ) (e.g., starting from 0 in each pwm cycle) or counting occurrences of matching continuously ( pd crb is used to enable/disable recount- ing occurrences of matching while pwm is on). 11.3.2 position detection circuit regist er functions pdcrc 5, 4 emem hold result of position detec- tion at pwm edge (detect position detected position) these bits hold the comparison result of position detection at falling or rising edge of pwm pulse. bits 5 and 4 are set to 1 when positi on is detected at the falling or the rising edge, respectively. they show whether position is detected in the current pwm pulse, during pwm off, or in the immediately preceding pwm pulse. 3 smon monitor sampling status when read, this bit shows the sampling status. 2 to 0 pdtct hold position signal input sta- tus this bit holds the status of the position signal input at the time position detection started in unmatch mode. pdcrb 7, 6 splck sampling period select fc/2 2 , fc/2 3 , fc/2 4 , or fc/2 5 for the position detection sampling period. 5, 4 splmd sampling mode select one of three modes: sampling only w hen pwm signal is active (when pwm is on), sampling regularly, or sampling when the lower side (x, y, z) phases are conducting cur- rent. 3 to 0 pdcmp sampling count in ordinary mode, when the port status a nd the set expected value match and continu- ously match as many times as the sampling counts set, a position detection signal is out- put and an interrupt is generated. in unmatch detection mode, when the said status and value do not match and continuously unmatch as many times as the sampling counts set, a position detection signal is output and an interrupt is generated. pdcra 7 swstp stop sampling in software sampling can be stopped in software by setting this bit to 1 (e.g., by writing to this regis- ter). sampling is performed before stopping and when position detection results match, a posi- tion detection interrupt is generated, with sampling thereby stopped. 6 swstt start sampling in software sampling can be started by sett ing this bit to 1 (e.g., by writing to this register). 5 sptm3 stop sampling using timer 3 sampling can be stopped by a trigger from timer 3 by setting this bit to 1. sampling is performed before stopping and when position detection results match, a posi- tion detection interrupt is generated, with sampling thereby stopped. 4 sttm2 start sampling using timer 2 sampling can be started by a trigger from timer 3 by setting this bit to 1. 3 pdnum number of position signal input pins select whether to use three pins (pdu/pdv/pdw) or one pin (pdu only) for position sig- nal input. when one pin is selected, the expected values of pdv and pdw are ignored. when performing position detection with two pins or a pin other than pdu, position signal input can be masked as 0 by se tting unused pin(s) for output. 2rcen recount occurrences of matching when pwm is on when performing sampling while pwm is on, occurrences of matching are recounted each time pwm signal turns on by setting th is bit to 1 (when recounting occurrences of matching, the count is reset each time pwm turns off). when this bit is set to 0, occur- rences of matching are counted cont inuously regardless pwm interval. 1 dtmd position detection mode setting this bit to 0 selects ordinary mode w here position is detected when the expected value set in the register and the port input unmatch and then match. setting this bit to 1 selects unmatch detection mode where position is detected at the time the port status changes to another one from the status in which it was when sampling started. 0 pdcen position detection function the position detection fu nction is activated by setting this bit to 1.
page 68 11. motor contro l circuit (pmd: programmable motor driver) TMP88PH40MG figure 11-5 position de tection sampling timing with the pwmon period selected figure 11-6 detection timing of the position de tection position sdreg 6 to 0 sdreg sampling delay set a time for which to stop sampling in orde r to prevent erroneous detection due to noise that occurs immediately after pwm output tu rns on (immediately after the transistor turns on). (figure 11-5)
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page 69 TMP88PH40MG note: when changing setting, keep the pdcen bit reset to ?0? (disable position detection function). note: read-modify-write instructions, such as a bit manipulatio n instruction, cannot access t he pdcra because it contains a write only bit. position detection circuit registers [addresses (pmd1)] pdcrc (01fa2h) 76543210 ? ? emem smon pdtct (initial value: **00 0000) 5, 4 emem hold result of position detection at pwm edge (detect position detected position) 00: detected in the current pulse 01: detected while pwm off 10: detected in the current pulse 11: detected in the preceding pulse r 3 smon monitor sampling status 0: sampling idle 1: sampling in progress 2 to 0 pdtct hold position signal input sta- tus holds the status of the position signal input during unmatch detection mode. bits 2 to 0 correspond to w, v, and u phases. pdcrb (01fa1h) 76543210 splck splmd pdcmp (initial value: 0000 0000) 7, 6 splck select sampling input clock 00: fc/2 2 [hz] (200 ns at 20 mhz) 01: fc/2 3 (400 ns at 20 mhz) 10: fc/2 4 (800 ns at 20 mhz) 11: fc/2 5 (1.6 s at 20 mhz) r/w 5, 4 splmd sampling mode 00: sample when pwm is on 01: sample regularly 10: sample when lower phases conducting current 11: reserved 3 to 0 pdcmp position detection matched counts 1 to 15 times (counts 0 and 1 are assumed to be one time.) pdcra (01fa0h) 76543210 swstp swstt sptm3 sttm2 pdnum rcen dtmd pdcen (initial value: 0000 0000) 7 swstp stop sampling in software 0: no operation 1: stop sampling w 6 swstt start sampling in software 0: no operation 1: start sampling 5 sptm3 stop sampling using timer 3 0: disable 1: enable r/w 4 sttm2 start sampling using timer 2 0: disable 1: enable 3 pdnum number of position signal input pins 0: compare three pins (pdu/pdv/pdw) 1: compare one pin (pdu) only 2 rcen recount occurrences of match- ing when pwm is on 0: continue counting from previously pwm on 1: recount each time pwm turns on 1 dtmd position detection mode 0: ordinary mode 1: unmatch detection mode 0 pdcen enable/disable position detec- tion function 0: disable 1: enable (sampling starts)
page 70 11. motor contro l circuit (pmd: programmable motor driver) TMP88PH40MG note: when changing setting, keep the pdcen bit reset to ?0? (disable position detection function). 11.3.3 outline processing in the position detection unit sdreg (01fa3h) 76543210 ? d6 d5 d4 d3 d2 d1 d0 (initial value: *000 0000) 6 to 0 sdreg sampling delay 2 3 /fc n bits (n = 0 to 6, maximum 50.8 s, resolution of 400 ns at 20 mhz) r/w

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page 71 TMP88PH40MG 11.4 timer unit figure 11-7 timer ci rcuit configuration the timer unit has an up counter (mode timer) which is cleared by a position detection interrupt (intpdc). using this counter, it can generate three types of timer interrup ts (inttmr1 to 3). these timer interrupts may be used to produce a commutation trigger, position detection start trigger, etc. also, the mode timer has a capture function which automatically captures register data in synchronism with position detection or overload protection. this cap- ture function allows motor revolutions to be calculated by measuring position detection intervals.

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page 72 11. motor contro l circuit (pmd: programmable motor driver) TMP88PH40MG 11.4.1 configuration of the timer unit the timer unit consists mainly of a mode timer, thr ee timer comparator, and mode capture register, and is controlled by timer control regist ers and timer compare registers. ? the mode timer can be reset by a signal from the position detection circuit, timer 3, or overload pro- tective circuit. if the mode timer overflows without being reset, it stops at ffffh and sets an overflow flag in the control register. ? the value of the mode timer during counting can be read by capturing the coun t in software and read- ing the capture register. ? timer 1 and timers 2 and 3 generate an interrup t signal by magnitude comparison and matching com- parison, respectively. therefore, timer 1 can genera te an interrupt signal even when it could not write to the compare register in time a nd the counter value at the time of writing happens to exceed the regis- ter?s set value. ? when any one of timers 1 to 3 interrupts occurs, the next interrupts can be enabled by writing a new value to the respective compare registers (cmp1, cmp2, cmp3). ? when capturing by position detection is enabled, the capture register has the timer value captured in it each time position is detected. in this way, the capture register always holds the latest value.
page 73 TMP88PH40MG 11.4.1.1 timer circuit register functions figure 11-8 dbout debug output diagram mtcrb 7 dbout debug output debug output can be produced by setting this bit to 1. because interrupt signals to the interrupt control circuit are used for each interrupt, hardware debugging without software delays are possible. see the debug output diagram (figure 11-8). output ports: p67 for pmd1. 5 tmof mode timer overflow this bit shows that the timer has overflowed. 3clcp capture mode timer by over- load protection when this bit is set to 1, the timer valu e can be captured using the overload protection signal (cl) as a trigger. 2swcp capture mode timer in soft- ware when this bit is set to 1, the timer value can be captured in software (e.g., by writing to this register). 1 pdccp capture mode timer by posi- tion detection when this bit is set to 1, the timer value can be captured using the position detection sig- nal as a trigger. mtcra 7, 6, 5 tmck select clock select the timer clock. 4rbtm3 reset mode timer from timer 3 when this bit is set to 1, the mode time r is reset by a trigger from timer 3. 3rbcl reset mode timer by over- load protection when this bit is set to 1, the mode timer is re set by the overload protection signal (cl) as a trigger. 2 swres reset mode timer in software when this bit is set to 1, the mode timer is rese t in software (e.g., by writing to this regis- ter) 1rbpdc reset mode timer by position detection when this bit is set to 1, the mode timer is re set by the position detection signal as a trig- ger. 0 tmen enable/disable mode timer the mode timer is started by setting this bit to 1. therefore, timers 1 to 3 must be set with cmp before setting this bit. if this bit is set to 0 after setting cmp, cmp settings become ineffective. mcap mode capture position detection interval can be read out. cmp1 timer 1 (commutation) timers 1 to 3 are enabled while the mode timer is operating. an interrupt can be gener- ated once by setting the corresponding bit in th is register. the interrupt is disable when an interrupt is generated or the timer is reset. to use the timer again, set the register back again even if data is same. cmp2 timer 2 (position detection start) cmp3 timer 3 (overflow)

page 74 11. motor contro l circuit (pmd: programmable motor driver) TMP88PH40MG note: read-modify-write instructions, such as a bit manipulation instruction, cannot access the mtcrb because it contains a write-only bit. note 1: when changing mtcra setting, keep the mt cra bit reset to ?0? (disable mode timer). note 2: read-modify-write instructions, such as a bit manipulation instruction, cannot access the mtcra because it contains a write-only bit. timer circuit registers [addresses (pmd1)] mtcrb (01fa5h) 76543210 dbout ? tmof ? clcp swcp pdccp ? (initial value: 0*0*0 000*) 7 dbout debug output 0: disable 1: enable (p67 for pmd1, p77 for pmd2) r/w 5 tmof mode timer overflow 0: no overflow 1: overflowed r 3clcp capture mode timer by over- load protection 0: disable 1: enable r/w 2 swcp capture mode timer in software 0: no operation 1: capture w 1 pdccp capture mode timer by position detection 0: disable 1: enable r/w mtcra (01fa4h) 76543210 tmck rbtm3 rbcl swres rbpdc tmen (initial value: 0000 0000) 7, 6, 5 tmck select clock 000: fc/2 3 (400 ns at 20 mhz) 010: fc/2 4 (800 ns at 20 mhz) 100: fc/2 5 (1.6 s at 20 mhz) 110: fc/2 6 (3.2 s at 20 mhz) 001: fc/2 7 (6.4 s at 20 mhz) 011: reserved 101: reserved 111: reserved r/w 4 rbtm3 reset mode timer from timer 3 0: disable 1: enable 3rbcl reset mode timer by overload protection 0: disable 1: enable 2 swres reset mode timer in software 0: no operation 1: reset w 1rbpdc reset mode timer by position detection 0: disable 1: enable r/w 0 tmen enable/disable mode timer 0: disable 1: enable timer start mcap (01fa7h, 01fa6h) fedcba9876543210 (initial value: 0000 0000 0000 0000) df de dd dc db da d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 mcap mode capture position detection interval r cmp1 (01fa9h, 01fa8h) fedcba9876543210 (initial value: 0000 0000 0000 0000) df de dd dc db da d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 cmp2 (01fabh, 01faah) fedcba9876543210 (initial value: 0000 0000 0000 0000) df de dd dc db da d9 d8 d7 d6 d5 d4 d3 d2 d1 d0
page 75 TMP88PH40MG note: read-modify-write instructions, such as a bit manipula tion instruction, cannot access the mtcrb or mtcra register because these registers contain write-only bits. 11.4.1.2 outline processing in the timer unit cmp3 (01fadh, 01fach) fedcba9876543210 (initial value: 0000 0000 0000 0000) df de dd dc db da d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 cmp1 timer 1 magnitude comparison compare register r/w cmp2 timer 2 matching comparison compare register cmp3 timer 3 matching comparison compare register

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page 76 11. motor contro l circuit (pmd: programmable motor driver) TMP88PH40MG 11.5 three-phase pwm output unit the three-phase pwm output unit has the function to generate three-phase pwm waves with any desired pulse width and the commutation function capable of brushless dc motor control. in addition, it has the protective func- tions such as overload prot ection and emergency stop functi ons necessary to protect th e power drive unit, and the dead time adding function which helps to prevent the in-phase upper/lower transistors from getting shorted by simul- taneous turn-on when switched over. for the pwm output pin (u,v,w,x,y,z), set the port register pxdr and pxcr (x = 3) to 1. the pwm output ini- tially is set to be active low, so that if the output need s to be used active high, set up the mdcra register accord- ingly. 11.5.1 configuration of th e three-phase pwm output unit the three-phase pwm output unit consists of a pulse width modulation circuit, commutation control circuit, protective circuit (emergency stop and over load), and a dead time control circuit. 11.5.1.1 pulse width modulation circuit (pwm waveform generating unit) this circuit produces three-phase independent pw m waveforms with an equal pwm frequency. for pwm waveform mode, triangular wave modulation or sawtooth wave modulation can be selected by using the pmd control register (mdcra) bit 1. the pwm frequency is set by using the pmd period register (mdprd). the following shows the relationshi p between the value of this register and the pwm counter clock set by the mdcrb register, pwmck. the pmd period register (mdprd) is comprised of dual-buffers, so that cmpu, v, w register is updated with pwm period. when the waveform arithmetic ci rcuit is operating, the pwm wavefo rm output unit r eceives calculation results from the waveform arithmetic circuit and by us ing the results as cmpu, v, w register set value, it outputs independent three-phase pwm waveforms. wh en the waveform calculati on function is enabled by the waveform arithmetic circuit and transfer of calculation results into the cmpu to w registers is enabled (with edcra register bit 2), the cmpu to w registers are disa bled against writing. when the waveform calculation func tion is enabled (with edcra regist er bit 1) and transfer of calcu- lation results into the cmpu, v, w registers is disabled (with edcra register bit 4), the calculation results are transferred to the buffers of cmpu, v, w registers, but not output to the port. read-accessing the cmpu, v, and w registers can read the calculation results of the waveform arith- metic circuit that have been input to a buffer. afte r changing the read calculation result data by software, writing the changed data to the cmpu, v, and w regi sters enables an arbitrar y waveform other than a sinusoidal wave to be output. when the registers are r ead after writing, the values written to the registers are read out if accessed before th e calculation results are transferre d after calculation is finished. triangular wave pwm: mdprd register set value 1 pwm frequency hz ] [ 2p wmck ---------------------------------------------------------------------------------------------- = sawtooth wave pwm: mdprd register set value 1 pwm frequency hz ] [ pwmck ------------------------------------------------------------------------------------ - =
page 77 TMP88PH40MG figure 11-9 pwm waveforms the values of the pwm compare registers (cmpu/v/ w) and the carrier wave generated by the pwm counter (mdcnt) are compared for the relative magnitude by the comparator to produce pwm wave- forms. the pwm counter is a 12-bit up/down counter with a 100 ns (at fc = 20 mhz) resolution. for three-phase output control, two methods of generating three-phase pwm waveforms can be set. 1. three-phase independent mode: values are set independently in the three-phase pmd compare registers to produce three-phase independent pwm waveforms. this method may be used to produce sinusoidal or any other desired drive waveforms. 2. three-phase common mode: a valu e is set in only the u-phase pmd compare register to pro- duce three in-phase pwm waveforms using the u ph ase set value. this method may be used for dc motor square wave drive. the three-phase pmd compare regist ers each have a comparison regi ster to comprise a dual-buffer structure. the values of the pmd co mpare registers are loaded into th eir respective comparison registers synchronously with pwm period.

page 78 11. motor contro l circuit (pmd: programmable motor driver) TMP88PH40MG 11.5.1.2 commutation control circuit output ports are controlled depending on the conten ts set in the pmd output register (mdout). the contents set in this register are divided into two, one for selecting the synchronizing signal for port output, and one for setting up port output. the synchronizing signal can be selected from timers 1 or 2, position detection signal, or without sync. port output can be synchronized to this synchronizing signal before being further synchronized to the pwm signal sync. the mdout register's synchronizing signal select bit becomes effective immediately after writing. othe r bits are dual-buffered, and are updated by the selected synchronizing signal. example: commutation timing for one timer period with pwm synchronization specified output on six ports can be set to be active high or active low independently of each other by using the mdcra register bits 5 and 4. furthermore, the u, v, and w phases can individu ally be selected between pwm output and h/l output by using the mdout register bits a to 8 and 5 to 0. when pwm output is selected, pwm waveforms are output; when h/l output is selected, a waveform which is fixed high or low is output. the mdout register bits e to c set the expected position sign al value for the position detection circuit. figure 11-10 pulse width modulation circuit inttmr pwm commutation 3 selector/ latch pwm control pwm interrupt intpwm clock selector pmd period register pmd compare register pwm counter pwm control register ? ? 3, 2, 1 7 60 mdcra b to 0 mdprd b to 0 mdcnt 1 to 0 mdcrb b to 0 cmpu b to 0 cmpw b to 0 cmpv buffer w buffer v buffer u selector/ latch three-phase common/ three-phase up/down pwmu pwmv pwmw stop mdcnt pwm synchronizing clock fc/2
page 79 TMP88PH40MG figure 11-11 commutation control circuit figure 11-12 d ead time circuit s selector s selector gate control set reset latch 6 3 2 mdout 5, 4, 3, 2, 1, 0 a, 9, 87, 6 ? b ? , ? , ? mdout sync fc/4 pwm synchronizing clock position detection interrupt intpdc timer 1 interrupt inttmr1 timer 2 interrupt inttmr2 pmd output register u x v y w z pwmu pwmv pwmw

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page 80 11. motor contro l circuit (pmd: programmable motor driver) TMP88PH40MG 11.5.2 register functions of the waveform synthesis circuit mdcrb pwmck select pwm counter cloc k select pwm counter clock. mdcra 7 hlfint select half-period interrupt when this bit is set to 1, intpwm is generated every half period (at triangular wave peak and valley) in the case of center pwm output and pint = 00. in other cases, this setting has no meaning. 6 dtymd duty mode select whether to set the duty cycle independent ly for three phases using the cmpu to w registers or in common for all three phases by setting the cmpu register only. 5 polh upper-phase port polarity select the upper-phase output port polarity. make sure the waveform synthesis function (mdcra register bit 0) is idle before selecting this port polarity. 4 poll lower-phase port polarity select the lower-phase output port polarity. make sure the waveform synthesis function (mdcra register bit 0) is idle before selecting this port polarity. 3, 2 pint pwm interrupt frequency select the frequency at which to generate a pwm interrupt from four choices available: every pwm period or once every 2, 4, or 8 pwm periods. when setting of this bit is altered while operating, an interrupt may be generated at the time the bit is altered. 1 pwmmd pwm mode select pwm mode. pwm mode 0 is an edge pwm (sawtooth wave), and pwm mode 1 is a center pwm (triangular wave). 0pwmen enable/disable waveform generation circuit when enabling this circuit (for waveform output), be sure to set the output port polarity and other bits of this register (other than mdcra bit 0) beforehand. dtr dtr dead time set the dead time between the upper-phase and lower-phase outputs. mdout f updwn pwm counter flag this bit indicates whether the pwm counter is counting up or down. when edge pwm (sawtooth wave) is selected, it is always set to 0. e, d, c pdexp mode compare register set the data to be compared with the position detection input port. the comparison data is adopted as the expected value simultaneously when port output sync settings made with mdout are reflected in the ports. (this is the expected position detection inpu t value for the output set with mdout next time.) b psync select pw m synchronization select whether or not to synchronize port output to pwm period after being synchronized to the synchronizing signal selected with syncs. if selected to be synchronized to pwm, output is kept waiting for the next pwm after being synchronized with syncs. waveform settings are overwritten if new settings are written to the register during this time, and out- put is generated with those settings. a 9 8 wpwm vpwm upwm control uvw-phase pwm outputs set u, v, and w-phase port outputs. (see the table 11-3) 7, 6 syncs select port output sync signal select the synchronizing signal with which to output uvw-phase settings to ports. the synchronizing signal can be selected from time rs 1 or 2, position detection, or asynchro- nous. select asynchronous when the initial setting, otherwise the above setting isn?t reflected immediately. 5, 4 3, 2 1, 0 woc voc uoc control uvw-phase outputs set u, v, and w-phase port outputs. (see the table 11-3) mdcnt pwm counter this is a 12-bit read-only register used to count pwm periods. mdprd set pwm period this register determines pwm period, and is dual-buffered, allowing pwm period to be altered even while the pwm counter is operating. the buffers are loaded every pwm period. when 100 ns is selected for the pwm counter clock, make sure the least signifi- cant bit is set to 0.
page 81 TMP88PH40MG note: when changing setting, keep the pwmen bit reset to ?0? (disable wave form synthesis function). note: when changing setting, keep the mdcr a bit reset to "0" (disabl e wave form synthesis function). cmpu cmpv cmpw set pwm pulse width this comparison register determines the pulse widths output in the respective uvw phases. this register is dual-buffered, and the pulse widths are determined by comparing the buffer and pwm counter. waveform synthesis circuit registers [addresses (pmd1)] mdcrb (01fafh) 76543210 ? ? ? ? ? ? pwmck (initial value: **** **00) 1, 0 pwmck pwm counterselect clock 00: fc/2 [hz] (100 ns at 20 mhz) 01: fc/2 2 (200 ns at 20 mhz) 10: fc/2 3 (400 ns at 20 mhz) 11: fc/2 4 (800 ns at 20 mhz) r/w mdcra (01faeh) 7654321 0 hlfint dtymd polh poll pint pwmmd pwmen (initial value: 0000 0000) 7 hlfint select half-period interrupt 0: interrupt as specified in pint 1: interrupt every half period when pint = 00 r/w 6 dtymd duty mode 0: u phase in common 1: three phases independent 5 polh upper-phase port polarity 0: active low 1: active high 4 poll lower-phase port polarity 0: active low 1: active high 3, 2 pint select pwm interrupt (trigger) 00: interrupt every period 01: interrupt once every 2 periods 10: interrupt once every 4 periods 11: interrupt once every 8 periods 1 pwmmd pwm mode 0: pwm mode0 (edge: sawtooth wave) 1: pwm mode1 (center: triangular wave) 0pwmen enable/disable waveform syn- thesis function 0: disable 1: enable (waveform output) dtr (01fbeh) 76543210 ? ? d5 d4 d3 d2 d1 d0 (initial value: **00 0000) 5 to 0 dtr dead time 2 3 /fc 6 bit (maximum 25.2 s at 20 mhz) r/w
page 82 11. motor contro l circuit (pmd: programmable motor driver) TMP88PH40MG 11.5.3 port output as set with uo c/voc/woc bits and up wm/vpwm/wpwm bits mdout (01fb3h, 01fb2h) fedcba98 updwn pdexp psync wpwm vpwm upwm 76543210 syncs woc voc uoc (initial value: 00000000 00000000) f updwn pwm counter flag 0: counting up 1: counting down r e, d, c pdexp comparison register for posi- tion detection bit e: w-phase expected value bit d: v-phase expected value bit c: u-phase expected value r/w b psync select pwm synchronization 0: asynchronous 1: synchronized a wpwm w-phase pwm output 0: h/l level output 1: pwm waveform output 9 vpwm v-phase pwm output 0: h/l level output 1: pwm waveform output 8 upwm u-phase pwm output 0: h/l level output 1: pwm waveform output 7, 6 syncs select port output synchronizing signal 00: asynchronous 01: synchronized to position detection 10: synchronized to timer 1 11: synchronized to timer 2 5, 4 woc control w-phase output see the table 1-3 3, 2 voc control v-phase output 1, 0 uoc control u-phase output table 11-3 example of pin output settings u-phase output polarity: active high (polh,poll = 1) u-phase output polarity: active low (polh,poll = 0) uoc upwm uoc upwm 1: pwm output 0: h/l level output 1: pwm output 0: h/l level output u phase x phase u phase x phas e u phase x phase u phase x phase 0 0 pwm pwm l l 0 0 pwm pwm hh 0 1 l pwm l h 0 1 h pwm hl 1 0 pwm l h l 1 0 pwm hlh 1 1 pwm pwm hh 1 1 pwm pwm l l
page 83 TMP88PH40MG mdcnt (01fb5h, 01fb4h) fedcba9876543210 (initial value: ****000000000000) ? ? ? ? dbdad9d8d7d6d5d4d3d2d1d0 b to 0 pwm counter pwm period counter value r mdprd (01fb7h, 01fb6h) fedcba9876543210 (initial value: ****000000000000) ? ? ? ? dbdad9d8d7d6d5d4d3d2d1d0 b to 0 pwm period pwm period mdprd 010h r/w cmpu (01fb9h, 01fb8h) fedcba9876543210 (initial value: ****000000000000) ? ? ? ? dbdad9d8d7d6d5d4d3d2d1d0 cmpv (01fbbh, 01fbah) fedcba9876543210 (initial value: ****000000000000) ? ? ? ? dbdad9d8d7d6d5d4d3d2d1d0 cmpw (01fbdh, 01fbch) fedcba9876543210 (initial value: ****000000000000) ? ? ? ? dbdad9d8d7d6d5d4d3d2d1d0 b to 0 cmpu pwm compare u register set u-phase duty cycle r/w cmpv pwm compare v register set v-phase duty cycle cmpw pwm compare w register set w-phase duty cycle
page 84 11. motor contro l circuit (pmd: programmable motor driver) TMP88PH40MG 11.5.4 protective circuit this circuit consists of an emg prot ective circuit and ov erload protective ci rcuit. these circ uits are activated by driving their respective port inputs active. figure 11-13 configuration of the protective circuit a. emg protective circuit this protective circuit is used for emergency st op, when the emg protec tive circuit is enabled. when the signal on emg input port goes active (negative edge triggered), the six ports are immedi- ately disabled high-impedance against output and an emg interrupt (intemg) is generated. the emg control register (emgcra) is used to set emg protection. if the emgcra shows the value ?1? when read, it means that the em g protective circuit is operating. to return from the emg protective state, reset the mdout register bits a to 0 and set the emgcra to 1. returning from the emg protectiv e state is effective when the emg protective input has been released back high. to disable the emg functio n, set data ?5ah? and ?a5h?sequentially in the emg disable register (emgrel) and reset th e emgcra to 0. when the emg func- tion is disabled, emg interrupt s (intemg) are not generated. the emg protective circuit is initially enabled. before disabling it, fully study on adequacy. b. overload protective circuit the overload protective circuit is set by using the emg control registers (emgcra/b). to acti- vate overload protection, set the emgcrb to 1 to enable the overlo ad protective circuit. the circuit starts operating when the overload protective input is pulled low. to return from overload st ate, there are three methods to use: return by a timer (emgcrb), return by pwm sync (emgcrb), or return manually (emgcrb). these methods are usable wh en the overload protective input has been released back high. cl detection reset control emg protective control timer 1 interrupt inttmr1 pwm synchronizing clock pwm sync overload protective interrupt intclm overload protective input cl stop mdcnt u x v y w z u' x' v' y' w' z' emg disable code register emg control register 210 ? 7, 6, 5, 4 emgcra 3, 2, 1, 0 7 emgcrb 4 6, 5 emgrel 7, 6, 5, 4, 3, 2, 1, 0 mdout a to 0 2 2 4 4 8 overload protective control set "0" emg emg input intemg emg interrupt under prote- ction
page 85 TMP88PH40MG the number of times the overload protective input is sampled can be set by using the emgcra. the sampling times can be set in the range of 1 to 15 times at 200 ns period (when fc = 20 mhz). if a low level is detected as many times as the specified number, overload pro- tection is assumed. the output disabled phases dur ing overload protection are set by using the emgcrb. this facility allows selecting to disable no phas es, all phases, pwm phases, or all upper phases/all lower phases. when selected to disable all upper phases/all lower phases, port output is determined by their turn-on status immediately before being disabled. when two or more upper phases are active, all upper phases are turned on and all lower phases are turned off; when two or more lower phases are active, all upper ph ases are turned off and all lower phases are turned on. when output phase are cut off, output is inactive (low in the ca se of high active). when the over- load protective circuit is disabled, overload pr otective interrupts (intclm) are not generated. figure 11-14 example of pr otection circuit operation

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page 86 11. motor contro l circuit (pmd: programmable motor driver) TMP88PH40MG 11.5.5 functions of prot ective circuit registers emgrel emg disable the emg protective circuit is disable from t he disabled state by writing ?5ah? and ?a5h? to this register in that order. after that, the emgcra register needs to be set. emgcrb 7rtcl return from overload protec- tive state when this bit is set to 1, the motor control ci rcuit is returned from overload protective state in software (e.g., by writing to this register). also, the current state can be known by read- ing this bit. mdout outputs at return from the overload protective state remain as set before the overload protective input was driven active. 6 rtpwm return by pwm sync when this bit is set to 1, the motor control ci rcuit is returned from overload protective state by pwm sync. if rtcl is set to 1, rtcl has priority. 5 rttm1 return by timer sync when this bit is set to 1, the motor control ci rcuit is returned from overload protective state by timer 1 sync. if rtcl is set to 1, rtcl has priority. 4 clst overload protective state the status of over load protection can be know n by reading this bit. 3, 2 clmd select output disabled phases during overload pro- tection select the phases to be disabled against out put during overload prot ection. this facility allows selecting to disable no phases, all pha ses, pwm phases, or all upper phases/all lower phases. 1cntst stop counter during overload protection can stop the pwm counter during overload protection. 0clen enable/disable overload pro- tection enable or disable the overload protective function. emgcra 7 to 4 clcnt overload protection sampling time set the length of time the overload protective input port is sampled. 2 emgst emg protective state the status of emg protection can be known by reading this bit. 1rte return from emg protective state the motor control circuit is returned from emg protective state by setting this bit to ?1? . when returning, set the mdout register a to 0 bits to ?0? . then set the emgcra reg- ister bit 1 to ?1? and set mdout waveform output. then set up the mdcra register. 0emgen enable/disable emg protec- tive circuit the emg protective circuit is activated by setting this bit to 1. this circuit initially is enabled. (to disable this circuit, make sure key code 5ah and a5h are written to the emgrel1 register beforehand.)
page 87 TMP88PH40MG note: read-modify-write instructions, such as a bit manipulation instruction, cannot access the emgrel register because this register is write only. note: if during overload protection the port output state in two or more upper phases is on, all lo wer phases are disabled and a ll upper phases are enabled for output; when two or more lowe r phases are on, all upper phases are disabled and all lower phases are enabled for output. note 1: an instruction specifying a return from the emg state is invalid if the emg input is ?l?. note 2: read-modify-write instructions, such as a bit manipulation instruction, cannot access the emgcrb or emgcra register because these registers c ontain write-only bits. protective circuit registers [addresses (pmd1)] emgrel (01fbfh) 76543210 d7 d6 d5 d4 d3 d2 d1 d0 (initial value: 0000 0000) 7 to 0 emgrel emg disable can disable by writing 5ah and then a5h. w emgcrb (01fb1h) 7654321 0 rtcl rtpwm rttm1 clst clmd cntst clen (initial value: 0000 0000) 7rtcl return from overload protec- tive state 0: no operation 1: return from protective state w 6rtpwm enable/disable return from overload protective state by pwm sync 0: disable 1: enable r/w 5 rttm1 enable/disable return from overload protective state by timer 1 0: disable 1: enable 4 clst overload protective state 0: no operation 1: under protection r 3, 2 clmd select output disabled phases during overload protection 00: no phases disabled against output 01: all phases disabled against output 10: pwm phases disabled against output 11: all upper/all lower phases disabled against output (note) r/w 1 cntst stop pwm counter during over- load protection 0: do not stop 1: stop the counter 0clen enable/disable overload pro- tective circuit 0: disable 1: enable emgcra (01fb0h) 7654321 0 clcnt emgst rte emgen (initial value: 0000 *001) 7 to 4 clcnt overload protection sampling number of times. 2 2 /fc n ( n = 1 to 15, 0 and 1 are set as 1 at 20 mhz ) r/w 2 emgst emg protective state 0: no operation 1: under protection r 1 rte return from emg state 0: no operation 1: return from protective state (note 1) w 0emgen enable/disable emg protective circuit 0: disable 1: enable r/w
page 88 11. motor contro l circuit (pmd: programmable motor driver) TMP88PH40MG 11.6 electrical angle timer and waveform arithmetic circuit electrical angle timer figure 11-15 electrical angle timer circuit waveform arithmetic circuit figure 11-16 waveform arithmetic circuit

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page 89 TMP88PH40MG 11.6.1 electrical angle timer and waveform arit hmetic circuit the electrical angle timer finishes counting upon reaching the value set by the period set register (edset). the electrical angle timer counts 360 degrees of electrical angle in the range of 0 to 383 (17fh) and is cleared to 0 upon reaching 383. in this way, it is possible to obtain the elect rical angle of the frequency proportional to the value set by the period set register. the period with which to count up can be corrected by using the period correction register, allowing for fine adjustment of the freque ncy. the electrical angles counted by the electrical angle timer are presented to the waveform arithmetic circuit. an electrical angle timer interrupt signal is gene rated each time the electrical a ngle timer finishes counting. the waveform arithmetic circuit has a sine wave data table, which is used to extract sine wave data based on the electrical angle data received fr om the electrical angle timer. this sine wave data is multiplied by the value of the voltage amplitude register. for 2-phase m odulation, the product obtained by this multiplication is presented to the waveform synthesis circuit. for 3-pha se modulation, waveform data is further calculated based on the product of multiplication and the electrical angle data and the value of the pwm period register. the calculation is performed each time the electrical angle timer finishes counting or when a value is set in the electrical angle regist er, and the calculation results consisting of the u phase, the v phase ( + 120 degrees), and the w phase ( + 240 degrees) are sequentially presented to the pwm waveform output circuit. the sine wave data table is stored in the ram and requires initialization. ? to correct the period, set the number of times ?n? to be corrected in the period correction register (edset register f to c bits). the period is corrected by adding 1 to electrical angle c ounts 16 for ?n? times. for example, when a value 3 is set in the period correction register, the period for 13 times out of electrical angle counts 16 is the value ?mh? set in the period set register, and that for 3 times is ?m + 1h?. (correction is made almost at equal intervals.) ? because the electrical angle count er (eldeg) can be accessed even while the electrical angle timer is operating, the electri cal angles can be corr ected during operation. ? the electrical angle capture ed cap captures the electrical angle value from the electrical angle counter at the time the position is detected. ? when the waveform calculation func tion is enabled, waveform calcu lation is performed each time the electrical angle counter (eldeg) ar e accessed for write or the electri cal angle timer finishes count- ing. ? the calculation is performed in 35 machine cycl e of execution time, or 7 s (at 20 mhz). ? when transfer of calculation result to the cmp registers is enabled (edcra), the calcula- tion results are transferred to the cmpu to w regi sters. (this applies only when the waveform calcu- lation function is enabled with the edcra.) the cmpu to w registers are disabled against write while the tran sfer remains enabled. the calculation re sults can be read from the cmpu to w registers while the waveform calculation function remains enabled. ? the calculated results can be modifi ed and the modified data can be se t in the cmpu to w registers in software. this makes it possible to output any desired waveform other than sine waves. if a transfer (edcra register bit 2) of the calculated results to th e cmp register is disabled, read- accessing the cmpu to w registers can read the calcu lated results. (before read-accessing these regis- ters, make sure that the calculation is completed.) ? to initialize the entire ram data of the sine wave da ta table, set the addresses at which to set, sequen- tially from 000h to 17fh, in the eldeg register, and write waveform data to the wfmdr register each time. make sure the waveform arithmetic circuit is disabled wh en writing this data. note 1: the value set in the period set register (edset register edt bits) must be equal to or greater than 010h. any value smaller than this is assumed to be 010h. note 2: the sine wave data that is read consists of t he u phase, the v phase whose electrical angle is +120 degrees relative to the u phase, and the w phase whose electrical angle is +240 degrees relative to the u phase. note 3: if a period corresponding to an electrical angle of on e degree is shorter than the required calculation time, the previously calculated results are used.
page 90 11. motor contro l circuit (pmd: programmable motor driver) TMP88PH40MG 11.6.1.1 functions of the electrical angle ti mer and waveform arithmetic circuit registers edcrb 3 calcst start calculation by software forcefully start calculation. when this bit is written while the waveform arithmetic circuit is calculating, the calculation is terminated and then newly started. 2 calcbsy calculation flag by reading this bit, the operation status of the waveform arithmetic circuit can be obtained. 1 edcalen enable/disable calculation start synchronized with elec- trical angle select whether to start calculation when the electrical angle timer finishes counting or when a value is set in the electrical angle r egister. when disabled, calculation is only started when calcst is set to 1. 0 edisel electrical angle interrupt set the electrical angle interrupt signal req uest timing to either when the electrical angle timer finishes counting or upon end of calculation. edcra 7 edcnt electrical angle count up/ down set whether the electrical angle timer counts up or down. 6 edrv select v-, w-phase select phase direction of v-phase and w-phase in relation to u-phase. 5, 4 edck select clock select the clock for the electrical angle time r. this setting can be altered even while the electrical angle timer is operating. 3 c2pen switch between 2-phase and 3-phase modulations select the modulation method with wh ich to perform waveform calculation. two-phase modulation data = ramdata (eldeg) amp note: the sign during 3-phase modulati on changes depending on the electrical angle. + for el ectrical angles 0 to 179 degrees (191) ? for electrical angles 180 (192) to 360 (383) degrees 2rwren auto transfer calculation results to cpm registers enable/disable transfer of calculation results by the waveform arithmetic circuit. when the waveform calculation function is enabled while at the same time transfer is enabled, cal- culation results are set as u, v, and w-phas e duty cycles of the pwm generation circuit and are reflected in the ports. 1calcen enable/disable waveform cal- culation function enable/disable the waveform calculation func tion. calculations are performed by the waveform arithmetic circuit by enabling the waveform calculation function. when the waveform calculation function is enabled, the calculated results can be read from the u, v, and w-phase compare registers (cmpu, v, w) of the pwm generation circuit. 0 edten electrical angle timer enable/disable the electrical angle timer. w hen enabled, the electrical angle timer starts counting; when disabled, the electrical angl e timer stops counting and is cleared to 0. edset f to c edth correct electrical angle period correct the period by adding 1 to electrical angl e counts 16 for ?n? times. the timer counts the electrical angle period set value ?m??for (16 ? n) times and counts (m + 1) for ?n? times b to 0 edt electrical angle period set the electrical angle period. eldeg electrical angle read the electrical angle. this register can also be set to initialize or correct the angle while counting. any value greater than 17fh cannot be set. amp set voltage amplitude set the voltage amplitude. the waveform arithmetic circuit multiplies the data set here by the sine wave data read out from the sine wave ram. the amplitude has its upper limit determined by the set value of the mdprd register when performing this multiplication. edcap capture electrical angle capture the value from the electrical angle timer when the position is detected. wfmdr set sine wave data to initialize the entire ram data of the sine wave table, set the addresses at which to set, sequentially from 000h to 17fh, in the eldeg register, and write waveform data to the wfmdr register each time. make sure the waveform arithmetic circuit is disabled when writing this data. three-phase modulation: data moprd 2 ---------------------- - ramdata eldeg () amp 2 -------------------------------------------------------------------- - =
page 91 TMP88PH40MG typical settings of sine wave data note: during 3-phase modulation, the sign changes at 180 degrees of electrical angle. figure 11-17 typical se ttings of sine wave data

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page 92 11. motor contro l circuit (pmd: programmable motor driver) TMP88PH40MG note: read-modify-write instructions, such as a bit manipulation instruction, cannot access the edcrb register because this reg- ister is write only. note: when changing the edcra setting, keep the edcra bit reset ?0? (disable electrical angle timer). list of the electrical angle timer and waveform arithmetic circuit registers [addresses (pmd1)] edcrb (01fc1h) 76543210 ? ? ? ? calcst calcbsy edcalen edisel (initial value: **** 0000) 3 calcst start calculation by software 0: no operation 1: start calculation w 2 calcbsy calculation flag 0: waveform arithmetic circuit stopped 1: waveform arithmetic circuit calculating r 1 edcalen enable/disable calculation start synchronized with electrical angle 0: start calculation insync with electrical angle 1: do notcalculation insync with electrical angle r/w 0 edisel electrical angle interrupt 0: interrupt when the electrical angle timer finishes counting 1: interrupt upon end of calculation edcra (01fc0h) 765432 1 0 edcnt edrv edck c2pen rwren calcen edten (initial value: 0000 0000) 7 edcnt electrical angle count up/down 0: count up 1: count down r/w 6 edrv select v-, w-phase 0: v = u + 120 , w = u + 240 1: v = u ? 120 , w = u ? 240 5, 4 edck select clock 00: fc/2 3 (400 ns at 20 mhz) 01: fc/2 4 (800 ns at 20 mhz) 10: fc/2 5 (1.6 s at 20 mhz) 11: fc/2 6 (3.2 s at 20 mhz) 3c2pen switch between 2-/3-phase modulations 0: 2-phase modulation 1: 3-phase modulation 2rwren transfer calculation result to cmp registers 0: disable 1: enable 1calc enable/disable waveform cal- culation function 0: disable 1: enable 0edten electrical angleenable/disable mode timer 0: disable 1: enable
page 93 TMP88PH40MG one period of the electrical angle timer, t, is expressed by the equation below. note: read-modify-write instructions, such as a bit manipulation instruction, cannot access the wfmdr register because this register is write only. edset (01fc3h, 01fc2h) fedcba9876543210 (initial value: 00000000 00010000) edth edt f to c edth correct period (n) 0 to 15 times r/w b to 0 edt set period (m) 010h eldeg (01fc5h, 01fc4h) fedcba9876543210 (initial value: *******0 00000000) ???????d8d7d6d5d4d3d2d1d0 8 to 0 eldeg electrical angle set the initially and the count values of electrical angle. r/w amp (01fc7h, 01fc6h) fedcba9876543210 (initial value: ****0000 00000000) ? ? ? ? dbdad9d8d7d6d5d4d3d2d1d0 b to 0 amp set voltage set the voltage to be used during waveform calculation. r/w edcap (01fc9h, 01fc8h) fedcba9876543210 (initial value: ******0 00000000) ???????d8d7d6d5d4d3d2d1d0 8 to 0 edcap captured value of electrical angle electrical angle timer val ue when position is detected. r wfmdr (01fcah) 76543210 d7 d6 d5 d4 d3 d2 d1 d0 (initial value: ********) 7 to 0 wfmdr sine wave data write sine wave data to ram of sine wave w tm n 16 ----- - + ?? ?? 384 set clock s [] where m set period, n period correction = = =
page 94 11. motor contro l circuit (pmd: programmable motor driver) TMP88PH40MG 11.6.1.2 list of pmd related control registers (1) input/output pins and input/output control registers pmd1 input/output pins (p3, p4) and port input/output control registers (p3cr, p4cr) note: when using these pins as pmd function or input port, set the output latch (p*dr) to 1. example of the pmd pin port setting name address bit r or w description p3dr 00003h 7 r/w overload protection ( cl1 ) 6 r/w emg input ( emg1 ) 5 to 0 r/w u1/v1/w1/x1/y1/z1 outputs. p4dr 00004h 2 to 0 r/w position signal inputs (pdu1, pdv1, pdw1). p3cr 01f89h 7 to 0 r/w p3 port input/output control (can be set bitwise). 0: input mode 1: output mode p4cr 01f8ah 2, 1, 0 r/w p0 port input/output control (can be set bitwise). 0: input mode 1: output mode input/output p3dr p3cr p4dr p4cr cl1 input * 0 ? ? emg1 input * 0 ? ? u1output11?? pdu1 input ? ? * 0
page 95 TMP88PH40MG (2) motor control circu it control registers [address : pmd1] position detection control register (pd cr) and sampling delay register (sdreg) name address bit r or w description pdcrc 01fa2h 5, 4 r detect the position-detected position. 00: within the current pulse 01: when pwm is off 10: within the current pulse 11: within the preceding pulse 3r monitor the sampling status. 0: sampling idle 1: sampling in progress 2 to 0 r holds the status of the position signal input during unmatch detection mode. bits 2, 1, and 0: w, v, and u phases pdcrb 01fa1h 7, 6 r/w select the sampling input clock [hz]. 00: fc/2 2 01: fc/2 3 10: fc/2 4 11: fc/2 5 5, 4 r/w sampling mode. 00: when pwm is on 01: regularly 10: when lower phases are turned on 3 to 0 r/w detection position match counts 1 to 15. pdcra 01fa0h 7w 0: no operation 1: stop sampling in software 6w 0: no operation 1: start sampling in software 5r/w stop sampling using timer 3. 0: disable 1: enable 4r/w start sampling using timer 2. 0: disable 1: enable 3r/w number of position signal input pins. 0: compare three pins (pdu/pdv/pdw) 1: compare one pin (pdu) only 2r/w count occurrences of matching when pwm is on. 0: subsequent to matching counts when pwm previously was on 1: eecount occurrences of matching each time pwm is on 1r/w position detection mode. 0: ordinary mode 1: unmatch detection mode 0r/w enable/disable position detection function. 0: disable 1: enable (sampling starts) sdreg 01fa3h 6 to 0 r/w sampling delay. 2 3 /fc n bits (n = 0 to 6, maximum 50.8 s at 20 mhz).
page 96 11. motor contro l circuit (pmd: programmable motor driver) TMP88PH40MG mode timer control register (mtcr), mode ca pture register (mcap), and compare registers (cmp1, cmp2, cmp3) name address bit r or w description mtcrb 01fa5h 7r/w debug output. 0: disable 1: enable (p67 for pmd1) 5r mode timer overflow. 0: no overflow 1: overflowed occurred 3r/w capture mode timer by overload protection. 0: disable 1: enable 2w capture mode timer by software. 0: no operation 1: capture 1r/w capture mode timer by position detection. 0: disable 1: enable mtcra 01fa4h 7, 6, 5 r/w select clock for mode timer [hz]. 000: fc/2 3 (400 ns at 20 mhz) 010: fc/2 4 (800 ns at 20 mhz) 100: fc/2 5 (1.6 s at 20 mhz) 110: fc/2 6 (3.2 s at 20 mhz) 001: fc/2 7 (6.4 s at 20 mhz) 011: reserved 101: reserved 111: reserved 4r/w reset timer by timer 3. 0: disable 1: enable 3r/w reset timer by overload protection. 0: disable 1: enable 2w reset timer by software. 0: no operation 1: reset 1r/w reset timer by position detection. 0: disable 1: enable 0r/w enable/disable mode timer. 0: disable 1: enable (timer starts) mcap 01fa7h, 01fa6h f to 0 r mode capture register. cmp1 01fa9h, 01fa8h f to 0 r/w compare register 1. cmp2 01fabh, 01faah f to 0 r/w compare register 2. cmp3 01fadh, 01fach f to 0 r/w compare register 3.
page 97 TMP88PH40MG pmd control register (mdcr), dead time register (dtr), and pmd output register (mdout) name address bit r or w description mdcrb 01fafh 1, 0 r/w select clock for pwm counter. 00: fc/2 (100 ns at 20 mhz) 01: fc/2 2 (200 ns at 20 mhz) 10: fc/2 3 (400 ns at 20 mhz) 11: fc/2 4 (800 ns at 20 mhz) mdcra 01faeh 7r/w select half-period interrupt 0: interrupt every period as specified in pint. 1: interrupt every half-period only pint=00. 6r/w duty mode. 0: u phase in common 1: three phases independent 5r/w upper-phase port polarity. 0: active low 1: active high 4r/w lower-phase port polarity. 0: active low 1: active high 3, 2 r/w select pwm interrupt (trigger). 00: interrupt once every period 01: interrupt once 2 periods 10: interrupt once 4 periods 11: interrupt once 8 periods 1r/w pwm mode. 0: pwm mode0 (edge: sawtooth wave) 1: pwm mode1 (center: triangular wave) 0r/w enable/disable waveform synthesis function. 0: disable 1: enable (waveform output) dtr 01fbeh 5 to 0 r/w set dead time. 2 3 /fc 6bit (maximum 25.2 s at 20 mhz). mdout 01fb3h, 01fb2h fr 0: count up 1: count down e, d, c r/w comparison register for position detection. 6: w 5: v 4: u br/w select pwm synchronization. 0: asynchronous with pwm period 1: synchronized ar/w w-phase pwm output. 0: h/l level output 1: pwm waveform output 9r/w v-phase pwm output. 0: h/l level output 1: pwm waveform output 8r/w u-phase pwm output. 0: h/l level output 1: pwm waveform output 7, 6 r/w select port output synchronizing signal. 00: asynchronous 01: synchronized to position detection 10: synchronized to timer 1 11: synchronized to timer 2 5, 4 r/w control w-phase output 3, 2 r/w control v-phase output 1, 0 r/w control u-phase output
page 98 11. motor contro l circuit (pmd: programmable motor driver) TMP88PH40MG pwm counter (mdcnt), pmd period regist er (mdprd), and pm d compare registers (cmpu, cmpv, cmpw) emg disable code register (emgrel) and emg control register (emgcr) name address bit r or w description mdcnt 01fb5h, 01fb4h b to 0 r read the pwm period counter value. mdprd 01fb7h, 01fb6h b to 0 r/w pwm period mdprd 010h. cmpu 01fb9h, 01fb8h b to 0 r/w set u-phase pwm duty cycle. cmpv 01fbbh, 01fbah b to 0 r/w set v-phase pwm duty cycle. cmpw 01fbdh, 01fbch b to 0 r/w set w-phase pwm duty cycle. name address bit r or w description emgrel 01fbfh 7 to 0 w code input for disable emg protection circuit. can be disable by writing 5ah and then a5h. emgcrb 01fb1h 7w return from overload protective state. 0: no operation 1: return from protective state 6r/w condition for returning from overload protective state: synchronized to pwm. 0: disable 1: enable 5r/w enable/disable return from overload protective state by timer 1. 0: disable 1: enable 4r overload protective state. 0: no operation 1: under protection 3, 2 r/w select output disabled phases during overload protection. 00: no phases disabled against output 01: all phases disabled against output 10: pwm phases disabled against output 11: all upper/all lower phases disabled against output 1r/w stop pwm counter (mdcnt) during overload protection. 0: do not stop 1: stop 0r/w enable/disable overload protective circuit. 0: disable 1: enable emgcra 01fb0h 7 to 4 r/w overload protection sampling time. 2 2 /fc n (n = 1 to 15, at 20 mhz) 2r emg protective state. 0: no operation 1: under protection 1w return from emg protective state. 0: no operation 1: return from protective state 0r/w enable/disable fanction of the emg protective circuit. 0: disable 1: enable (this circuit initially is enabled (= 1) . to disable this circuit, make sure key code 5ah and a5h are written to the emgrel1 register before- hand.)
page 99 TMP88PH40MG electrical angle control register (edcr), electrical angle peri od register (e dset), electrical angle set register (eldeg), voltage set regist er (amp), and electrical angle capture register (edcap). name address bit r or w description edcrb 01fc1h 3w 0: no operation 1: start calculation 2r 0: waveform arithmetic circuit stopped 1: waveform arithmetic circuit calculatin 1r/w 0: start calculation insync with electrical angle 1: do not calculation insync with electrical angle 0r/w 0: interrupt when the electrical angle timer finishes counting 1: interrupt upon end of calculation edcra 01fc0h 7r/w 0: count up 1: count down 6r/w 0: v = u + 120 , w = u + 240 1: v = u ? 120 , w = u ? 240 5, 4 r/w select clock. 00: fc/2 3 01: fc/2 4 10: fc/2 5 11: fc/2 6 3r/w switch between 2/3-phase modulations. 0: two-phase modulation 1: three-phase modulation 2r/w transfer calculation result to cmp registers. 0: disable 1: enable 1r/w enable/disable waveform calculation function. 0: disable 1: enable 0r/w electrical angle timer. 0: disable 1: enable edset 01fc3h, 01fc2h f to c r/w correct period (n) 0 to 15 times. b to 0 r/w set period (1/m counter) 010h eldeg 01fc5h, 01fc4h 8 to 0 r/w initially set and count values of electrical angle. amp 01fc7h, 01fc6h b to 0 r/w set voltage used during waveform calculation. edcap 01fc9h, 01fc8h 8 to 0 r electrical angle timer value when position is detected. wfmdr 01fcah 7 to 0 w set sine wave data.
page 100 11. motor contro l circuit (pmd: programmable motor driver) TMP88PH40MG
page 101 TMP88PH40MG 12. asynchronous serial interface (uart) the TMP88PH40MG has a asynchron ous serial interface (uart) . it can connect the peripheral circuits through txd and rxd pin. txd and rxd pin are also used as the general port. for txd pin, the corresponding gene ral port should be set output mode (set its output control register to "1" after its output port latch to "1"). for rxd pin, should be set input mode. this uart and sio can not us e simultaneously because their input/output ports are common. 12.1 configuration figure 12-1 uart (asynch ronous serial interface) counter y a b c s s a b c d y e f g h uart status register uart control register 2 uart control register 1 transmit data buffer receive data buffer fc/13 fc/26 fc/52 fc/104 fc/208 fc/416 fc/96 stop bit parity bit fc/2 6 fc/2 7 fc/2 8 baud rate generator transmit/receive clock 2 4 3 2 2 2 noise rejection circuit m p x transmit control circuit shift register shift register receive control circuit mpx: multiplexe r uartcra tdbuf rdbuf inttx intrx uartsr uartcrb rxd txd inttc4
page 102 12. asynchronous serial interface (uart) 12.2 control TMP88PH40MG 12.2 control uart is controlled by the uart control registers ( uartcra, uartcrb). the operating status can be moni- tored using the uart status register (uartsr). note 1: when operations are disabled by setting uartcra bits to ?0?, the setting becomes valid when data transmit or receive complete. when the transmit data is stor ed in the transmit data buffer, the data are not transmitted. even if data transmit is enabled, until new data are written to the transmit data buffer, the current data are not transmitted. note 2: the transmit clock and the parity are common to transmit and receive. note 3: uartcra and uartcra should be set to ?0? before uartcra is changed. note 4: in case fc = 20mhz, the timer counter 4 (tc4) is available as a baud rate generator. note: when uartcrb = ?01?, pulses longer than 96 /fc [s] are always regarded as signals; when uart- crb = ?10?, longer than 192/fc [s]; and when uartcrb = ?11?, longer than 384/fc [s]. uart control register1 uartcra (01f91h) 76543210 txe rxe stbt even pe brg (initial value: 0000 0000) txe transfer operation 0: 1: disable enable write only rxe receive operation 0: 1: disable enable stbt transmit stop bit length 0: 1: 1 bit 2 bits even even-numbered parity 0: 1: odd-numbered parity even-numbered parity pe parity addition 0: 1: no parity parity brg transmit clock select 000: 001: 010: 011: 100: 101: 110: 111: fc/13 [hz] fc/26 fc/52 fc/104 fc/208 fc/416 input inttc4 fc/96 uart control register2 uartcrb (01f92h) 7654321 0 rxdnc stopbr (initial value: **** *000) rxdnc selection of rxd input noise rejectio time 00: 01: 10: 11: no noise rejection (hysteresis input) rejects pulses shorter than 31/fc [s] as noise rejects pulses shorter than 63/fc [s] as noise rejects pulses shorter than 127/fc [s] as noise write only stopbr receive stop bit length 0: 1: 1 bit 2 bits
page 103 TMP88PH40MG note: when an inttxd is generated, tbep flag is set to "1" automatically. uart status register uartsr (01f91h) 76543210 perr ferr oerr rbfl tend tbep (initial value: 0000 11**) perr parity error flag 0: 1: no parity error parity error read only ferr framing error flag 0: 1: no framing error framing error oerr overrun error flag 0: 1: no overrun error overrun error rbfl receive data buffer full flag 0: 1: receive data buffer empty receive data buffer full tend transmit end flag 0: 1: on transmitting transmit end tbep transmit data buffer empty flag 0: 1: transmit data buffer full (transmit data writing is finished) transmit data buffer empty uart receive data buffer rdbuf (01f93h) 76543210read only (initial value: 0000 0000) uart transmit data buffer tdbuf (01f93h) 76543210write only (initial value: 0000 0000)
page 104 12. asynchronous serial interface (uart) 12.3 transfer data format TMP88PH40MG 12.3 transfer data format in uart, an one-bit start bit (low level), stop bit (bit length selectable at high level, by uartcra), and parity (select parity in uart cra; even- or odd-numbered parity by uartcra) are added to the transfer data. the transfer da ta formats are shown as follows. figure 12-2 tran sfer data format figure 12-3 caution on c hanging transfer data format note: in order to switch the transfer data format, perfor m transmit operations in the above figure 12-3 sequence except for the initial setting. start bit 0 bit 1 bit 6 bit 7 stop 1 start bit 0 bit 1 bit 6 bit 7 stop 1 stop 2 start bit 0 bit 1 bit 6 bit 7 parity stop 1 start bit 0 bit 1 bit 6 bit 7 parity stop 1 stop 2 pe 0 0 1 1 stbt frame length 0 1 123 89101112 0 1 without parity / 1 stop bit with parity / 1 stop bit without parity / 2 stop bit with parity / 2 stop bit
page 105 TMP88PH40MG 12.4 transfer rate the baud rate of uart is set of uartcra. th e example of the baud rate are shown as follows. when inttc4 is used as the uart transfer rate (whe n uartcra = ?110?), the transfer clock and trans- fer rate are determined as follows: transfer clock [hz] = tc4 sour ce clock [hz] / tc4dr setting value transfer rate [baud] = transfer clock [hz] / 16 12.5 data sampling method the uart receiver keeps sampling input using the cl ock selected by uartcra until a start bit is detected in rxd pin input. rt clock star ts detecting ?l? level of the rxd pin. once a start bit is detected, the start bit, data bits, stop bi t(s), and parity bit are sampled at three times of rt7, rt8, and rt9 during one receiver clock interval (rt clock). (rt0 is the position where the bit supposedly starts.) bit is determined according to majority rule (the data are the same twice or more out of three samplings). figure 12-4 data sampling method table 12-1 transfer rate (example) brg source clock 16 mhz 8 mhz 000 76800 [baud] 38400 [baud] 001 38400 19200 010 19200 9600 011 9600 4800 100 4800 2400 101 2400 1200 rt0 1 2 3 4 5 6 7 8 9101112 1314 15 01234567891011 bit 0 start bit bit 0 start bit (a) without noise rejection circuit rt clock internal receive data rt0 1 2 3 4 5 6 7 8 9101112 1314 15 01234567891011 bit 0 start bit bit 0 start bit rt clock internal receive data (b) with noise rejection circuit rxd pin rxd pin
page 106 12. asynchronous serial interface (uart) 12.6 stop bit length TMP88PH40MG 12.6 stop bit length select a transmit stop bit length (1 bit or 2 bits) by uartcra. 12.7 parity set parity / no parity by uartcra and set parity type (odd- or even-numbered) by uartcra. 12.8 transmit/receive operation 12.8.1 data transmit operation set uartcra to ?1?. read ua rtsr to check uartsr = ?1 ?, then write data in tdbuf (transmit data buffer). writing data in tdbuf zero-cl ears uartsr, transfers the data to the transmit shift register and the data are sequenti ally output from the txd pin. the data output include a one-bit start bit, stop bits whose number is specified in uartcra and a parity bit if parity addition is specified. select the data transfer baud rate using uartcra. when data transmit starts, transmit buffer empty flag uartsr is set to ?1? a nd an inttxd interrupt is generated. while uartcra = ?0? and from when ?1? is wr itten to uartcra to when send data are written to tdbuf, the txd pin is fixed at high level. when transmitting data, first read uartsr, then write data in tdbuf. otherwise, uartsr is not zero-cleared and transm it does not start. 12.8.2 data receive operation set uartcra to ?1?. when data are received vi a the rxd pin, the receive data are transferred to rdbuf (receive data buffer). at this time, the data transmitted includes a start bit and stop bit(s) and a parity bit if parity addition is specified. when stop bit(s) are received, data only are extracted and transferred to rdbuf (receive data buffer). then the receive buffer full flag ua rtsr is set and an intrxd interrupt is generated. select the data transfer baud rate using uartcra. if an overrun error (oerr) occurs when data are received, the da ta are not transferre d to rdbuf (receive data buffer) but discarded; data in the rdbuf are not affected. note:when a receive operation is disabled by setting ua rtcra bit to ?0?, the setting becomes valid when data receive is completed. however, if a framing error occurs in data receive, the receive-disabling setting may not become valid. if a framing error occurs , be sure to perform a re-receive operation.
page 107 TMP88PH40MG 12.9 status flag 12.9.1 parity error when parity determined using the receive data bits diff ers from the received parity bit, the parity error flag uartsr is set to ?1?. the uartsr is cl eared to ?0? when the rdbuf is read after read- ing the uartsr. figure 12-5 generati on of parity error 12.9.2 framing error when ?0? is sampled as the stop bit in the receive data, framing error flag uartsr is set to ?1?. the uartsr is cleared to ?0? when the rdbuf is r ead after reading the uartsr. figure 12-6 generati on of framing error 12.9.3 overrun error when all bits in the next data are received while unread data are still in rdbuf, overrun error flag uartsr is set to ?1?. in this case, the receive data is discarded; data in rdbuf are not affected. the uartsr is cleared to ?0? when the rdbuf is read af ter reading the uartsr. parity stop shift register pxxxx0 * 1pxxxx0 xxxx0 ** rxd pin uartsr intrxd interrupt after reading uartsr then rdbuf clears perr. final bit stop shift register xxxx0 * 0xxxx0 xxx0 ** rxd pin uartsr intrxd interrupt after reading uartsr then rdbuf clears ferr.
page 108 12. asynchronous serial interface (uart) 12.9 status flag TMP88PH40MG figure 12-7 generati on of overrun error note:receive operations are di sabled until the overrun error flag uartsr is cleared. 12.9.4 receive data buffer full loading the received data in rdbuf sets receive data buffer full flag uartsr to "1". the uartsr is cleared to ?0? when the rdbuf is read after reading the uartsr. figure 12-8 generat ion of receive data buffer full note:if the overrun error flag uartsr is set during the period between reading the uartsr and reading the rdbuf, it cannot be cleared by only reading the rdbuf. therefore, after reading the rdbuf, read the uartsr again to check whether or not the overrun er ror flag which should have been cleared still remains set. 12.9.5 transmit data buffer empty when no data is in the transmit buffer tdbuf, that is, when data in tdbuf are transferred to the transmit shift register and data transmit starts, transmit data buffer empty flag uartsr is set to ?1?. the uartsr is cleared to ?0 ? when the tdbuf is writte n after reading the uartsr. final bit stop shift register xxxx0 * 1xxxx0 yyyy xxx0 ** rxd pin uartsr intrxd interrupt after reading uartsr then rdbuf clears oerr. rdbuf uartsr final bit stop shift register xxxx0 * 1xxxx0 xxxx yyyy xxx0 ** rxd pin uartsr intrxd interrupt rdbuf after reading uartsr then rdbuf clears rbfl.
page 109 TMP88PH40MG figure 12-9 generation of transmit data buffer empty 12.9.6 transmit end flag when data are transmitted and no data is in tdbuf (uartsr = ?1?), transmit end flag uartsr is set to ?1?. the uartsr is cleared to ?0? when the data transmit is stated after writing the tdbuf. figure 12-10 generation of transmit end flag and transmit data buffer empty shift register data write data write zzzz xxxx yyyy start bit 0 final bit stop 1xxxx0 ***** 1 * 1xxxx **** 1x ***** 1 1yyyy0 tdbuf txd pin uartsr inttxd interrupt after reading uartsr writing tdbuf clears tbep. shift register * 1yyyy *** 1 xx **** 1 x ***** 1 stop start 1yyyy0 bit 0 txd pin uartsr uartsr inttxd interrupt data write for tdbuf
page 110 12. asynchronous serial interface (uart) 12.9 status flag TMP88PH40MG
page 111 TMP88PH40MG 13. synchronous serial interface (sio) the TMP88PH40MG has a clocked-synchron ous 8-bit serial interface. serial interface has an 8-byte transmit and receive data buffer that can automatically and continuously transfer up to 64 bits of data. serial interface is connected to outside peripherl devices via so, si, sck port. this sio and uart can not use simultaneously because their input/out put ports are common. 13.1 configuration figure 13-1 serial interface sio control / status register serial clock shift clock shift register 3 2 1 0 7 6 5 4 transmit and receive data buffer (8 bytes in dbr) control circuit cpu serial data output serial data input 8-bit transfer 4-bit transfer serial clock i/o buffer control circuit so si sck siocr2 siocr1 siosr intsio interrupt request
page 112 13. synchronous serial interface (sio) 13.2 control TMP88PH40MG 13.2 control the serial interface is controlled by sio control registers (s iocr1/siocr2). the serial interface status can be determined by reading sio status register (siosr). the transmit and receive data buffer is controlled by the siocr2. th e data buffer is assigned to address 01f98h to 01f9fh for sio in the dbr area, and can continuo usly transfer up to 8 words (bytes or nibbles) at one time. when the specified number of words has been transferre d, a buffer empty (in the tran smit mode) or a buffer full (in the receive mode or tr ansmit/receive mode) interrup t (intsio) is generated. when the internal clock is used as the serial clock in the 8-bit receive mode and the 8-bit transmit/receive mode, a fixed interval wait can be applied to the serial clock fo r each word transferred. four different wait times can be selected with siocr2. note 1: fc; high-frequency clock [hz] note 2: set siocr1 to "0" and siocr1 to "1" when setting the transfer mode or serial clock. note 3: siocr1 is write-only register, whic h cannot access any of in read-modify-wri te instruction such as bit operate, etc. sio control register 1 siocr176543210 (1f96h) sios sioinh siom sck (initial value: 0000 0000) sios indicate transfer start / stop 0: stop write only 1: start sioinh continue / abort transfer 0: continuously transfer 1: abort transfer (automatically cleared after abort) siom transfer mode select 000: 8-bit transmit mode 010: 4-bit transmit mode 100: 8-bit transmit / receive mode 101: 8-bit receive mode 110: 4-bit receive mode except the above: reserved sck serial clock select normal, idle mode write only dv1ck = 0 dv1ck = 0 000 fc/2 13 fc/2 14 001 fc/2 8 fc/2 9 010 fc/2 7 fc/2 8 011 fc/2 6 fc/2 7 100 fc/2 5 fc/2 6 101 fc/2 4 fc/2 5 110 reserved 111 external clock (input from sck pin) sio control register 2 siocr276543210 (1f97h) wait buf (initial value: ***0 0000)
page 113 TMP88PH40MG note 1: the lower 4 bits of each buffer are used during 4-bit tr ansfers. zeros (0) are stored to the upper 4bits when receiving. note 2: transmitting starts at the lowest address. received data are also stored starting from the lowest address to the highest address. ( the first buffer address transmitted is 01f98h ). note 3: the value to be loaded to buf is held after transfer is completed. note 4: siocr2 must be set when the serial interface is stopped (siof = 0). note 5: *: don't care note 6: siocr2 is write-only register, whic h cannot access any of in read-modify-wri te instruction such as bit operate, etc. note 7: t f ; frame time, t d ; data transfer time figure 13-2 fr ame time (t f ) and data transfer time (t d ) note 1: after siocr1 is cleared to "0", siosr is cleared to "0" at the termination of transfer or the setting of siocr1 to "1". 13.3 serial clock 13.3.1 clock source internal clock or external clock for the source clock is selected by siocr1. wait wait control always sets "00" except 8-bit transmit / receive mode. write only 00: t f = t d (non wait) 01: t f = 2t d (wait) 10: t f = 4t d (wait) 11: t f = 8t d (wait) buf number of transfer words (buffer address in use) 000: 1 word transfer 01f98h 001: 2 words transfer 01f98h ~ 01f99h 010: 3 words transfer 01f98h ~ 01f9ah 011: 4 words transfer 01f98h ~ 01f9bh 100: 5 words transfer 01f98h ~ 01f9ch 101: 6 words transfer 01f98h ~ 01f9dh 110: 7 words transfer 01f98h ~ 01f9eh 111: 8 words transfer 01f98h ~ 01f9fh sio status register siosr76543210 (1f97h) siof sef (initial value: 00** ****) siof serial transfer operating status moni- tor 0: 1: transfer terminated transfer in process read only sef shift operating status monitor 0: 1: shift operation terminated shift operation in process td tf (output) s ck output
page 114 13. synchronous serial interface (sio) 13.3 serial clock TMP88PH40MG 13.3.1.1 internal clock any of six frequencies can be selected. the serial clock is output to the outside on the sck pin. the sck pin goes high when transfer starts. when data writing (in the transmit mo de) or reading (in the receive mode or the transmit/receive mode) cannot keep up with the serial clock rate, there is a wa it function that automatically stops the serial clock and holds the next shift operation until the read/write processing is completed. note: 1 kbit = 1024 bit (fc = 20 mhz) figure 13-3 automatic wait fu nction (at 4-bit transmit mode) 13.3.1.2 external clock an external clock connected to the sck pin is used as the serial clock. in this case, the sck (p43) port should be set to input mode. to ensure shifting, a pulse width of more than 2 4 /fc is required. this pulse is needed for the shift operation to ex ecute certainly. actually, there is necessary processi ng time for inter- rupting, writing, and reading. the minimum pulse is determined by setting the mode and the program. figure 13-4 external clock pulse width table 13-1 serial clock rate normal, idle mode sck clock baud rate 000 fc/2 13 2.44 kbps 001 fc/2 8 78.13 kbps 010 fc/2 7 156.25 kbps 011 fc/2 6 312.50 kbps 100 fc/2 5 625.00 kbps 101 fc/2 4 125.00 kbps 110 - - 111 external external a 1 a 2 b 0 b 1 b 2 b 3 c 0 c 1 a 3 a c b a 0 pin (output) pin (output) written transmit data a utomat i ca ll y wait function sck so t sckl t sckh t sckl , t sckh > 2 4 /fc sck pin (input)
page 115 TMP88PH40MG 13.3.2 shift edge the leading edge is used to transmit, a nd the trailing edge is used to receive. 13.3.2.1 leading edge transmitted data are shifted on the leading ed ge of the serial clock (falling edge of the sck pin input/ output). 13.3.2.2 trailing edge received data are shifted on the trailing edge of the serial clock (rising edge of the sck pin input/out- put). figure 13-5 shift edge 13.4 number of bits to transfer either 4-bit or 8-bit serial transfer can be selected. when 4-bit serial transfer is selected, only the lower 4 bits of the transmit/receive data buffer re gister are used. the upper 4 bits are cleared to ?0? when receiving. the data is transferred in sequence star ting at the least significant bit (lsb). 13.5 number of w ords to transfer up to 8 words consisting of 4 bits of data (4-bit serial tran sfer) or 8 bits (8-bit serial tr ansfer) of data can be trans- ferred continuously. the number of words to be transferred can be selected by siocr2. an intsio interrupt is generated when the specified number of words has been transferred. if the number of words is to be changed during transfer , the serial interface must be stopped before making the ch ange. the number of words can be changed during automatic-wa it operation of an internal clock. in this case, the serial interface is not required to be stopped. bit 1 bit 2 bit 3 * 321 3210 ** 32 *** 3 bit 0 shift register shift register bit 1 bit 0 bit 2 bit 3 0 *** **** 210 * 10 ** 3210 (a) leading edge (b) trailing edge * ; don?t care so pin si pin sck pin sck pin
page 116 13. synchronous serial interface (sio) 13.6 transfer mode TMP88PH40MG figure 13-6 number of words to transfer (example: 1word = 4bit) 13.6 transfer mode siocr1 is used to select the tr ansmit, receive, or tr ansmit/receive mode. 13.6.1 4-bit and 8-bit transfer modes in these modes, firstly set the sio control register to the transmit mode, and then write first transmit data (number of transfer words to be transfer red) to the data buffer registers (dbr). after the data are written, the transmission is star ted by setting siocr1 to ?1?. the data are then output sequentially to the so pin in synchronous with th e serial clock, starting with the least significant bit (lsb). as soon as the lsb has been output, the data are transferred from the data buffer register to the shift register. when the final data bit has been transferred a nd the data buffer register is empty, an intsio (buffer empty) interrupt is generated to request the next transmitted data. when the internal clock is used, the serial clock will stop and an automatic-wait will be initiated if the next transmitted data are not loaded to the data buffer regist er by the time the number of data words specified with the siocr2 has been transmitted . writing even one word of data can cels the automatic- wait; therefore, when transmitting two or more words, always write the ne xt word before transmission of the previous word is completed. note:automatic waits are also canceled by writing to a dbr not being used as a transmit data buffer register; there- fore, during sio do not use such dbr for other applicati ons. for example, when 3 words are transmitted, do not use the dbr of the remained 5 words. when an external clock is used, the data must be writte n to the data buffer register before shifting next data. thus, the transfer speed is determin ed by the maximum delay time from the generation of the interrupt request to writing of the data to the data buffer register by the interrupt service program. the transmission is ended by clearing siocr1 to ?0? or setting siocr1 to ?1? in buffer empty interrupt service program. a 1 a 2 a 3 a 0 a 1 a 2 a 3 b 0 b 1 b 2 b 3 c 0 c 1 c 2 c 3 a 0 a 1 a 0 a 2 a 3 b 0 b 1 b 2 b 3 c 0 c 1 c 2 c 3 (a) 1 word transmit (b) 3 words transmit (c) 3 words receive so pin intsio interrupt intsio interrupt intsio interrupt so pin si pin sck pin sck pin sck pin
page 117 TMP88PH40MG siocr1 is cleared, the operation will end after all bits of words are transmitted. that the transmission has ended can be determined from the status of siosr becau se siosr is cleared to ?0? when a transfer is completed. when siocr1 is set, the transmission is immediately ended and siosr is cleared to ?0?. when an external clock is used, it is also necessary to clear siocr1 to ?0? before shifting the next data; if siocr1 is not cleared before shift out, dummy data will be transmitted and the operation will end. if it is necessary to change the number of word s, siocr1 should be cleared to ?0?, then siocr2 must be rewritten after confirming that siosr has been cleared to ?0?. figure 13-7 transfer m ode (example: 8bit, 1word tr ansfer, internal clock) figure 13-8 transfer mode (example: 8b it, 1word transfer , external clock) a 1 a 2 a 3 a 4 a 5 a 6 a 7 b 0 b 1 b 2 b 3 b 4 b 5 b 6 b 7 a 0 dbr b a clear sios write (a) write (b) sck pin (output) so pin intsio interrupt siocr1 siosr siosr siosr a 1 a 2 a 3 a 4 a 5 a 6 a 7 b 0 b 1 b 2 b 3 b 4 b 5 b 6 b 7 a 0 dbr b a clear sios write (a) write (b) sck pin (input) so pin intsio interrupt siocr1 siosr siosr
page 118 13. synchronous serial interface (sio) 13.6 transfer mode TMP88PH40MG figure 13-9 transmiiied data ho ld time at end of transfer 13.6.2 4-bit and 8- bit receive modes after setting the control registers to the receive mode , set siocr1 to ?1? to enable receiving. the data are then transferred to the shift register via the si pin in synchronous with the serial clock. when one word of data has been received, it is tran sferred from the shift register to the data buffer register (dbr). when the number of words specified w ith the siocr2 has been received, an intsio (buffer full) interrupt is generated to request that these data be read out. the da ta are then read from the da ta buffer registers by the interrupt service program. when the internal clock is used, and the previous data are not read from the data buffer register before the next data are received, the serial cloc k will stop and an automatic-wait will be initiated until the data are read. a wait will not be initiated if even one data word has been read. note:waits are also canceled by readi ng a dbr not being used as a received data buffer register is read; therefore, during sio do not use such dbr for other applications. when an external clock is used, the shift operation is synchronized with the extern al clock; therefore, the previous data are read before the next data are transferred to the data buffer register. if the previous data have not been read, the next data will not be transferred to th e data buffer register and th e receiving of any more data will be canceled. when an external clock is used, th e maximum transfer speed is determined by the delay between the time when the interrupt request is gene rated and when the data received have been read. the receiving is ended by clearing si ocr1 to ?0? or setting sio cr1 to ?1? in buffer full interrupt service program. when siocr1 is cleared, th e current data are transferred to the buffer. after siocr1 cleared, the receiving is ended at the ti me that the final bit of the data has been received. that the receiving has ended can be determined from the st atus of siosr. siosr is cleared to ?0? when the receiv- ing is ended. after confirmed the r eceiving termination, the final receiving data is read. when siocr1 is set, the receiving is immediately ended and si osr is cleared to ?0 ?. (the received data is ignored, and it is not required to be read out.) if it is necessary to change the number of words in external clock operation, siocr1 should be cleared to ?0? then siocr2 mu st be rewritten after confirming th at siosr ha s been cleared to ?0?. if it is necessary to change the number of words in internal clock, during automatic-wait operation which occurs after completion of data recei ving, siocr2 must be rewritten before the received data is read out. note:the buffer contents are lost when the transfer mode is switched. if it should become necessary to switch the transfer mode, end receiving by cl earing siocr1 to ?0?, read the last data and then switch the trans- fer mode. msb of last word t sodh = min 3.5/fc [s] (in the normal, idle modes) sck pin so pin siosr
page 119 TMP88PH40MG figure 13-10 receive mode (example: 8b it, 1word transfer, internal clock) 13.6.3 8-bit trans fer / receive mode after setting the sio control register to the 8-bit transmit/recei ve mode, write the data to be transmitted first to the data buffer registers (dbr). after that, enable the transmit/receive by sett ing siocr1 to ?1?. when transmitting, the data are output from the so pin at leading edges of the serial clock. when receiving, the data are input to the si pin at th e trailing edges of the serial clock. wh en the all receive is enabled, 8-bit data are transferred from th e shift register to the data buffer regist er. an intsio interrupt is generated when the number of data words specified with the siocr2 has been tr ansferred. usually, read the receive data from the buffer register in the interrupt service. the data buffer register is used for both transmitting and receiving; therefore, always writ e the data to be transmitted af ter reading the all received data. when the internal clock is used, a wait is initiated until the received data are read and the next transfer data are written. a wait will not be initiated if ev en one transfer data word has been written. when an external clock is used, the shift operation is synchronized with the external clock; therefore, it is necessary to read the received data and write the data to be transmitted next before starting the next shift oper- ation. when an external clock is us ed, the transfer speed is determined by the maximum delay between genera- tion of an interrupt request and the received data are read and the data to be transmitted next are written. the transmit/receive operatio n is ended by clearing siocr1 to ?0? or setting siocr1 to ?1? in intsio interrupt service program. when siocr1 is cleared, the current data ar e transferred to the buff er. after siocr1 cleared, the transmitting/ receiving is ended at the time that the fi nal bit of the data has been transmitted. that the transmitting/ receiving has ended can be determined from the status of siosr. siosr is cleared to ?0? when the transmitting/recei ving is ended. when siocr1 is set, the transmit/receive operation is immediately ended and siosr is cleared to ?0?. if it is necessary to change the number of words in external clock operation, siocr1 should be cleared to ?0?, then sio cr2 must be rewritten after confirmi ng that siosr has been cleared to ?0?. if it is necessary to change the number of words in internal clock, during automatic-wait operation which occurs after completion of transmit/ receive operation, siocr2 must be rewritten before reading and writing of the receive/transmit data. a 1 a 0 a 2 a 3 a 4 a 5 a 6 a 7 b 0 b 1 b 2 b 3 b 4 b 5 b 6 b 7 dbr b a clear sios read out read out sck pin (output) si pin intsio interrupt siocr1 siosr siosr
page 120 13. synchronous serial interface (sio) 13.6 transfer mode TMP88PH40MG note:the buffer contents are lost when the transfer mode is switched. if it should become necessary to switch the transfer mode, end receiving by cl earing siocr1 to ?0?, read the last data and then switch the trans- fer mode. figure 13-11 transfer / receive mode (examp le: 8bit, 1word transfe r, internal clock) figure 13-12 transmitted data hold ti me at end of tr ansfer / receive a 1 a 0 a 2 a 3 a 4 a 5 a 6 a 7 b 0 b 1 b 2 b 3 b 4 b 5 b 6 b 7 c 1 c 0 c 2 c 3 c 4 c 5 c b c 6 c 7 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 clear sios dbr d a read out (c) write (a) read out (d) write (b) sck pin (output) so pin intsio interrupt siocr1 siosr siosr si pin bit 7 of last word bit 6 t sodh = min 4/fc [s] (in the normal, idle modes) sck pin so pin siosr
page 121 TMP88PH40MG 14. 10-bit ad converter (adc) the TMP88PH40MG have a 10-bit successive approximation type ad converter. 14.1 configuration the circuit configuration of the 10-bit ad converter is shown in figure 14-1. it consists of control register adccra and adccrb, converted value register adcdrh and adcdrl, a da converter, a sample-hold circuit, a compar ator, and a successive comparison circuit. note: before using ad converter, set appropriate value to i/o port register conbining a analog input port. for details, see the sec- tion on "i/o ports". figure 14-1 10-bit ad converter 2 4 10 8 ainds adrs r/2 r/2 r ack amd irefon ad conversion result register 1, 2 ad converter control register 1, 2 adbf eocf intadc sain n successive approximate circuit adccrb adcdrh adcdrl adccra sample hold circuit a s en shift clock da converter analog input multiplexer y reference voltage analog comparator 2 3 control circuit avss varef avdd ain0 ain3
page 122 14. 10-bit ad converter (adc) 14.2 register configuration TMP88PH40MG 14.2 register configuration the ad converter consists of the following four registers: 1. ad converter control register 1 (adccra) this register selects the analog channels and operatio n mode (software start or repeat) in which to per- form ad conversion and controls the ad converter as it starts operating. 2. ad converter control register 2 (adccrb) this register selects the ad conversion time and co ntrols the connection of the da converter (ladder resistor network). 3. ad converted value register 1 (adcdrh) this register used to store the digital value after being converted by the ad converter. 4. ad converted value register 2 (adcdrl) this register monitors the oper ating status of the ad converter. note 1: select analog input channel during ad converter stops (adcdrl = "0"). note 2: when the analog input channel is all use di sabling, the adccra should be set to "1". note 3: during conversion, do not perform port output instruction to maintain a precision for all of the pins because analog inp ut port use as general input port. and for port near to anal og input, do not input intense signaling of change. note 4: the adccra is automatically cleared to "0" after starting conversion. note 5: do not set adccra newly again during ad c onversion. before setting adccra newly again, check adcdrl to see that the conversion is completed or wait until the interrupt signal (intadc) is generated (e.g., interrupt handling routine). note 6: after reset, adccra is initialized reserved setti ng. therfore, set the appropriate analog input channel to adc- cra when use ad converter. note 7: after adccra is set to 00h, ad conversion can not be star ted for four cycles. thus, four nops must be inserted before setting the adccra. ad converter control register 1 adccra (0026h) 76543210 adrs amd ainds sain (initial value: 0001 0000) adrs ad conversion start 0: 1: - ad conversion start r/w amd ad operating mode 00: 01: 10: 11: ad operation disable software start mode reserved repeat mode ainds analog input control 0: 1: analog input enable analog input disable sain analog input channel select 0000: 0001: 0010: 0011: 0100: 0101: 0110: 0111: 1000: 1001: 1010: 1011: 1100: 1101: 1110: 1111: ain0 ain1 ain2 ain3 reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved
page 123 TMP88PH40MG note 1: always set bit0 in adccrb to "0" and set bit4 in adccrb to "1". note 2: when a read instruction for adccrb, bit6 to 7 in adccrb read in as undefined data. note 1: setting for " ? " in the above table are inhibited. fc: high frequency oscillation clock [hz] note 2: set conversion time setting should be kept more than the following time by analog reference voltage (varef). ad converter control register 2 adccrb (0027h) 76543210 irefon "1" ack "0" (initial value: **0* 000*) irefon da converter (ladder resistor) connection control 0: 1: connected only during ad conversion always connected r/w ack ad conversion time select (refer to the following table about the con- version time) 000: 001: 010: 011: 100: 101: 110: 111: 39/fc reserved 78/fc 156/fc 312/fc 624/fc 1248/fc reserved table 14-1 ack setting and conversion time (at cgcr="0") condition conversion time 20 mhz 16 mhz 8 mhz ack 000 39/fc - - - 001 reserved 010 78/fc - - - 011 156/fc - - 19.5 s 100 312/fc 15.6 s 19.5 s 39.0 s 101 624/fc 31.2 s 39.0 s 78.0 s 110 1248/fc 62.4 s 78.0 s 156.0 s 111 reserved table 14-2 ack setting and conversion time (at cgcr="1") condition conversion time 20 mhz 16 mhz 8 mhz ack 000 39/fc - - - 001 reserved 010 78/fc - - - 011 156/fc - - 19.5 s 100 312/fc 15.6 s 19.5 s 39.0 s 101 624/fc 31.2 s 39.0 s 78.0 s 110 1248/fc 62.4 s 78.0 s 156.0 s 111 reserved - varef = 4.5 to 5.5 v 15.6 s and more
page 124 14. 10-bit ad converter (adc) 14.2 register configuration TMP88PH40MG note 1: the adcdrl is cleared to "0" when reading the ad cdrh. therfore, the ad conversion result should be read to adcdrl more first than adcdrh. note 2: the adcdrl is set to "1" when ad conversion starts, and cleared to "0" when ad conversion finished. note 3: if a read instruction is executed for a dcdrl, read data of bit3 to bit0 are unstable. ad converted value register 1 adcdrh (0029h) 76543210 ad09 ad08 ad07 ad06 ad05 ad04 ad03 ad02 (initial value: 0000 0000) ad converted value register 2 adcdrl (0028h) 76543210 ad01 ad00 eocf adbf (initial value: 0000 ****) eocf ad conversion end flag 0: 1: before or during conversion conversion completed read only adbf ad conversion busy flag 0: 1: during stop of ad conversion during ad conversion
page 125 TMP88PH40MG 14.3 function 14.3.1 software start mode after setting adccra to ?01? (software start mode), set adccra to ?1?. ad conver- sion of the voltage at the analog input pin specified by adccra is thereby started. after completion of the ad conversion, the conversion result is stored in ad converted value registers (adcdrh, adcdrl) and at the same time adcdrl is set to 1, the ad conversion finished inter- rupt (intadc) is generated. adrs is automatically cleared afte r ad conversion has started. do not set adccra newly again (restart) during ad convers ion. before setting adccra newly again, check adcdrl to see that the conversion is completed or wait until the interrupt signal (intadc) is generated (e.g., interrupt handling routine). figure 14-2 software start mode 14.3.2 repeat mode ad conversion of the voltage at the analog input pin specified by adccra is performed repeat- edly. in this mode, ad conver sion is started by setting adccra to ?1? after setting adc- cra to ?11? (repeat mode). after completion of the ad conversion, the conversion result is stored in ad converted value registers (adcdrh, adcdrl) and at the same time adcdrl is set to 1, the ad conversion finished inter- rupt (intadc) is generated. in repeat mode, each time one ad conversion is complete d, the next ad conversion is started. to stop ad conversion, set adccra to ?00? (disable mode) by writing 0s. the ad convert operation is stopped immediately. the converted valu e at this time is not stored in the ad converted value register. adcdrh status eocf cleared by reading conversion result conversion result read adcdrl intadc interrupt request adcdrl adccra 1st conversion result 2nd conversion result indeterminate ad conversion start ad conversion start a dcdrh a dcdrl conversion result read conversion result read conversion result read
page 126 14. 10-bit ad converter (adc) 14.3 function TMP88PH40MG figure 14-3 repeat mode 14.3.3 regi ster setting 1. set up the ad converter control register 1 (adccra) as follows: ? choose the channel to ad convert using ad input channel select (sain). ? specify analog input enable fo r analog input control (ainds). ? specify amd for the ad converter control operation mode (software or repeat mode). 2. set up the ad converter control register 2 (adccrb) as follows: ? set the ad conversion time using ad conversion time (ack). for details on how to set the con- version time, refer to figure 14-1, figure 14-2 and ad converter control register 2. ? choose irefon for da converter control. 3. after setting up (1) and (2) above, set ad conversion start (adrs) of ad converter control register 1 (adccra) to ?1?. if software start mode has been selected, ad conversi on starts immediately. 4. after an elapse of the specified ad conversion time, the ad converted value is stored in ad con- verted value register 1 (adcdrh) and the ad conv ersion finished flag (e ocf) of ad converted value register 2 (adcdrl) is set to ?1?, upon which time ad conversion interrupt intadc is gen- erated. 5. eocf is cleared to ?0? by a read of the conversion result. however, if reconverted before a register read, although eocf is cl eared the previous conversi on result is retained until the next conversion is completed. a dcdrh,adcdrl eocf cleared by reading conversion result conversion result read a dcdrl intadc interrupt request conversion operation a dccra indeterminate ad conversion start adccra ?11? ?00? 1st conversion result ad convert operation suspended. conversion result is not stored. 2nd conversion result 3rd conversion result a dcdrh a dcdrl 2nd conversion result 3rd conversion result 1st conversion result conversion result read conversion result read conversion result read conversion result read conversion result read
page 127 TMP88PH40MG example :after selecting the conversion time 15.6 s at 20 mhz and the analog input channel ain4 pin, perform ad con- version once. after checking eocf, read the converted valu e, store the lower 2 bits in address 0009eh and store the upper 8 bits in address 0009fh in ram. the operation mode is software start mode. : (port setting) : ;set port register approrriately before setting ad converter registers. : : (refer to section i/o port in details) ld (adccra) , 00100100b ; select software start mode, analog input enable, and ain4 ld (adccrb) , 00011000b ;select conversion time(312/fc) and operation mode set (adccra) . 7 ; adrs = 1(ad conversion start) sloop : test (adcdrb) . 5 ; eocf= 1 ? jrs t, sloop ld a , (adcdrl) ; read result data ld (9eh) , a ld a , (adcdrh) ; read result data ld (9fh), a
page 128 14. 10-bit ad converter (adc) 14.4 analog input voltage and ad conversion result TMP88PH40MG 14.4 analog input voltage and ad conversion result the analog input voltage is corresponded to the 10-bit dig ital value converted by the ad as shown in figure 14-4. figure 14-4 analog i nput voltage and ad c onversion result (typ.) 1 0 01 h 02 h 03 h 3fd h 3fe h 3ff h 2 3 1021 1022 1023 1024 analog input voltage 1024 ad conversion result varef avss
page 129 TMP88PH40MG 14.5 precautions about ad converter 14.5.1 analog input pin voltage range make sure the analog input pins (ain0 to ain3) are used at voltages within varef to avss. if any voltage outside this range is applied to one of the analog input pins, the converted value on that pin becomes uncertain. the other analog input pins also are affected by that. 14.5.2 analog input shared pins the analog input pins (ain0 to ain3) are shared w ith input/output ports. when using any of the analog inputs to execute ad conversion, do not execute input/output instructions for all other ports. this is necessary to prevent the accuracy of ad conversi on from degrading. not only these analog input sh ared pins, some other pins may also be affected by noise arising from input/o utput to and from adjacent pins. 14.5.3 noise countermeasure the internal equivalent circuit of the analog input pins is shown in figure 14-5. the higher the output impedance of the analog input source, more easily they are susceptible to no ise. therefore, make sure the out- put impedance of the signal source in your design is 5 k ? or less. toshiba also recommends attaching a capac- itor external to the chip. figure 14-5 analog i nput equivalent circuit and exam ple of input pin processing da converter aini analog comparator internal resistance permissible signal source impedance internal capacitance 5 k ? (typ) c = 22 pf (typ.) 5 k ? (max) note) i = 3 to 0
page 130 14. 10-bit ad converter (adc) 14.5 precautions about ad converter TMP88PH40MG
page 131 TMP88PH40MG 15. otp operation this section describes the funstion and basic opera tionalblocks of TMP88PH40MG. the TMP88PH40MG has prom in place of the mask rom which is included in th e tmp88ch40mg. the config uration and function are the same as the tmp88ch40mg. in addition, TMP88PH40MG op erates as the single clock mode when releasing reset. 15.1 operating mode the TMP88PH40MG has mcu mode and prom mode. 15.1.1 mcu mode the mcu mode is set by fixing the test/vpp pin to the low level. (test/vpp pin cannot be used open because it has no built-in pull-down resistor). 15.1.1.1 program memory the TMP88PH40MG has 16k bytes built-in one-tim e-prom (addresses 4000 to 7effh and fff00 to fffffh in the mcu mode, addresses 0000 to 3fffh in the prom mode). when using TMP88PH40MG for evaluation of mask rom products, the program is written in the pro- gram storing area shown in figure 15-1. since the TMP88PH40MG supports several mask ro m sizes, check the differ ence in memory size and program storing area between the one-time prom and the mask rom to be used. figure 15-1 prog ram memory area note: the area that is not in use should be set data to ffh, or a general-purpose prom programmer should be set only in the program memory area to access. 15.1.1.2 data memory TMP88PH40MG has a built-in 512 bytes + 128 bytes data memory (static ram). 15.1.1.3 input/output circuiry 1. control pins the control pins of the TMP88PH40MG are the same as those of the tmp88ch40mg except that the test pin does not have a built-in pull-down resistor. 2. i/o ports mask rom sfr ram dbr reserved program area reserved vector table area 00000 00040 002bf 04000 07eff fff00 fffff mcu mode sfr ram dbr reserved reserved 00000 00040 002bf 04000 07eff fff00 fffff prom mode 00000 03f00 03fff 03eff to to program area program area vector table area vector table area
page 132 15. otp operation 15.1 operating mode TMP88PH40MG the i/o circuitries of the TMP88PH40MG i/ o ports are the same as those of the tmp88ch40mg. 15.1.2 prom mode the prom mode is set by setting the reset pin, test pin and other pins as shown in table 15-1 and fig- ure 15-1. the programming and verification for the in ternal prom is acheived by using a general-purpose prom programmer with the adaptor socket. note 1: the high-speed program mode can be used. the setti ng is different according to the type of prom pro- grammer to use, refer to each description of prom programmer. TMP88PH40MG does not support the electric signat ure mode, apply the rom type of prom programmer to tc571000d/ad. always set the adapter socket switch to the "n" side when using toshiba?s adaptor socket. table 15-1 pin name in prom mode pin name (prom mode) i/o function pin name (mcu mode) a16 input program memory address input p60 a15 to a8 input program memory address input p37 to p30 a7 to a0 input program memory address input p37 to p30 d7 to d0 input/output program memory data input/output p37 to p30 ce input chip enable signal input p62 oe input output enable signal input p63 pgm input program mode signal input p61 dids input prom mode control signal input p42 vpp power supply +12.75v/5v (power supply of program) test vcc power supply +6.25v/5v vdd gnd power supply 0v vss vcc setting pin fix to "h" level in prom mode avdd,p41,p44 gnd setting pin fix to "l" level in prom mode avss,varef,p40,p43,p45,p10 reset setting pin fix to "l" level in prom mode reset xin (clk) input set oscillation with resonator in case of external clk input, set clk to xin and set xout to open. xin xout output xout
page 133 TMP88PH40MG note 1: eprom adaptor socket (tc571000 ? 1m bit eprom) note 2: prom programmer connection adaptor sockets bm11695 for TMP88PH40MG note 3: inside pin name for TMP88PH40MG note 4: outside pin name for eprom figure 15-2 prom mode setting v cc xin xout ce oe refer to pin function for the other pin setting. vss test v pp (12.5 v/5 v) a16 g nd pgm dids v cc setting pins gnd setting pins a15 a7 d7 to to to a8 a0 d0 to TMP88PH40MG p60 p37 p30 p62 p63 p61 p42 20 mhz
page 134 15. otp operation 15.1 operating mode TMP88PH40MG 15.1.2.1 programming flowchart (high-speed program writing) figure 15-3 prog ramming flowchart the high-speed programming mode is set by applying vpp=12.75v (programming voltage) to the vpp pin when the vcc = 6.25 v. after th e address and data are fixed, the data in the address is written by applying 0.1[msec] of low level program pulse to pgm pin. then verify if the data is written. if the programmed data is incorrect, a nother 0.1[msec] pulse is applied to pgm pin. this programming procedure is repeated until correct data is r ead from the address (maximum of 25 times). subsequently, all data are programmed in all address. when all data were written, verfy all address under the condition vcc=vpp=5v. v cc = 6.25 v yes no error verify n = 25? ok start v pp = 12.75 v address = start address n = 0 program 0.1 ms pulse n = n + 1 last address ? yes v cc = 5 v v pp = 5 v read all data ok address = address + 1 no pass fail error
page 135 TMP88PH40MG 15.1.2.2 program writing using a general-purpose prom programmer 1. recommended otp adaptor bm11695 for TMP88PH40MG 2. setting of otp adaptor set the switch (sw1) to "n" side. 3. setting of prom programmer a. set prom type to tc571000d/ad. vpp: 12.75 v (high-speed program writing mode) b. data transmission ( or copy) (note 1) the prom of TMP88PH40MG is located on di fferent address; it depends on operating mode: mcu mode and prom mode. when you write the data of rom for mask rom prod- ucts, the data shuold be transferred (or copied ) from the address for mcu mode to that for prom mode before writing operation is execute d. for the applicable program areas of mcu mode and prom mode are different, refer to TMP88PH40MG" figure 15-1 program mem- ory area ". example: in the block transfer (copy) mode, executed as below. 16kb rom capacity: 04000 to 07effh + fff00 to fffffh 00000~03fffh c. setting of the program address (note 1) start address: 00000h end address: 03fffh 4. writting write and verify according to the above procedure "setting of prom programmer". note 1: for the setting method, refer to each description of prom programmer. make sure to set the data of address area that is not in use to ffh. note 2: when setting mcu to the adaptor or when setting the adaptor to the prom programmer, set the first pin of the adaptor and that of prom programmer sock et matched. if the first pin is conversely set, mcu or adaptor or programmer would be damaged. note 3: the TMP88PH40MG does not support the electric signature mode. if prom programmer uses the signature, the de vice would be damaged because of applying voltage of 12 0.5v to pin 9(a9) of the address. don?t use the signature.
page 136 15. otp operation 15.1 operating mode TMP88PH40MG
page 137 TMP88PH40MG 16. input/output circuitry 16.1 control pins the input/output circuitries of the TMP88PH40MG control pins are shown below. note: the test pin of tmp88ph40 does not have a pull-down resistor (r in ) and protect diode (d1). fix the test pin at ?l? level in mcu mode. control pin i/o input/output circuitry remark xin xout input output high-frequency resonator connecting pins r f = 1.2 m ? (typ.) r o = 0.5 k ? (typ.) reset input hysteresis input pullup resistor included r in = 220 k ? (typ.) test input without pull-down resistor fix the test pin at ?l? level in mcu mode. fc r f r o osc. enable xin xout vdd vdd
page 138 16. input/output circuitry 16.2 input/output ports TMP88PH40MG 16.2 input/output ports port i/o input/output circuit remark p3 p4 i/o tri-state output programmable open-drain p3, p4: large-current port hysteresis input p6 i/o tri-state output p1 i/o tri-state output hysteresis input initial "high-z" disable output control data output pin input initial "high-z" disable data output pin input initial "high-z" disable data output pin input
page 139 TMP88PH40MG 17. electrical characteristics 17.1 absolute maximum ratings the absolute maximum ratings stipulat e the standards, any parameter of which cannot be exceeded even in an instant. if the device is used under conditions exceed ing the absolute maximum ratings, it may break down or degrade, causing injury due to rupture or burning. therefore, always make sure the absolute maximum ratings will not be exceeded when designin g your application equipment. (v ss = 0 v) parameter symbol pins standard unit remarks power supply voltage v dd ? 0.3 to 6.5 v program voltage v pp test/v pp ? 0.3 to 13.0 input voltage v in ? 0.3 to v dd + 0.3 output voltage v out ? 0.3 to v dd + 0.3 output current i oh p1, p3, p4, p6 ? 1.8 ma i ol1 p1, p6 3.2 i ol2 p3, p4 30 mean output current i out1 p1, p6 16 total of all ports except large-current ports i out2 p3 60 total of 8 pins of large-current ports p30 to 37 i out3 p4 60 total of 6 pins of large-current ports p40 to 45 power dissipation p d TMP88PH40MG 180 mw sop operating temperature topr ? 40 to 85 c soldering temperature (time) tsld 260 (10 s) c storage temperature tstg ? 55 to 125 c
page 140 17. electrical characteristics 17.3 dc characteristics TMP88PH40MG 17.2 operating conditions the operating conditions show the conditions under which the device be used in orde r for it to operate normally while maintaining its quality. if the device is used outsid e the range of operating conditions (power supply voltage, operating temperature range, or ac/dc rated values), it may operate erratically. therefore, when designing your application equipment, always make sure its intended working conditio ns will not exceed th e range of operating conditions. 17.3 dc characteristics note 1: typical values show those at topr = 25 c, vdd = 5v. note 2: input current (i in3 ); the current through pull-up or pull-down resistor is not included. note 3: i dd does not include i ref current. (v ss = 0 v, topr = ? 40 to 85 c) parameter symbol pins condition min max unit power supply voltage v dd fc = 20 mhz normal/idle 4.5 5.5 v high level input voltage v ih1 normal (p6) v dd 4.5 v v dd 0.70 v dd v v ih2 hysteresis (p1, p3, p4, reset ) v dd 0.75 low level input voltage v il1 normal (p6) v dd 4.5 v 0 v dd 0.30 v v il2 hysteresis (p1, p3,p4, reset ) v dd 0.25 clock frequency fc xin, xout v dd = 4.5 v to 5.5 v 820mhz (v ss = 0 v, topr = ? 40 to 85 c) parameter symbol pins condition min typ. max unit input current i in1 test v dd = 5.5 v, v in = 5.5 v/0 v ?? 2 a i in2 sink open drain, tri-state i in3 reset input resistance r in2 reset 90 220 510 k ? output leakage current i lo1 sink open drain v dd = 5.5 v, v in = 0.0 v ??2 a i lo2 tri-state port v dd = 5.5 v, v in = 5.5 v/0 v ?? 2 high level output voltage v oh tri-state port v dd = 4.5 v, i oh = ? 0.7 ma 4.1 ? ? v low level output voltage i ol1 p1, p6 v dd = 4.5 v, v ol = 0.4 v 1.6 ? ? ma i ol2 p3, p4 v dd = 4.5 v, v ol = 1.0 v ?20? normal mode power supply current i dd v dd = 5.5 v, v in = 5.3 v/0.2 v fc = 20 mhz ?1316 idle mode power supply current ?1012
page 141 TMP88PH40MG 17.4 ad conversi on characteristics note 1: the total error includes all errors except a quantizat ion error, and is defined as a maximum deviation from the idea conversion line. note 2: conversion time is different in recommended value by power supply voltage. about conversion time, please refer to "register c onfiguration" in the section of ad converter. note 3: please use input voltage to ain input pin in limit of v aref - v ss . when voltage or range outside is input, conversion value becomes unsettled and gives affect to other channel conversion value. note 4: analog reference voltage range; ? v aref = v aref - v ss note 5: when ad converter is not used, fix the avdd and varef pin on the , v dd level. 17.5 ac characteristics (topr = ? 40 to 85 c) parameter symbol condition min typ. max unit 8 bit 10 bit analog reference voltage v aref v ss = 0 v, v dd = av dd v dd ? 1.0 ? v dd v analog input voltage range v ain v ass ? v aref analog reference power supply current i ref v dd = av dd = v aref = 5.0 v v ss = av ss = 0 v ?0.5 1.0 ma nonlinearity error v dd = 5 v, v ss = 0 v av dd = v aref = 5 v av ss = 0 v ?? 1 2 lsb zero error ?? 1 2 full scale error ?? 1 2 overall error ?? 2 4 (v ss = 0 v, v dd = 4.5 to 5.5 v, topr = ? 40 to 85 c) parameter symbol condition min typ. max unit machine cycle time tcy during normal mode 0.2 ? 0.5 s during idle mode high level clock pulse width t wch when operating with external clock (xin input) fc = 20 mhz ?25?ns low level clock pulse width t wcl
page 142 17. electrical characteristics 17.5 ac characteristics TMP88PH40MG 17.6 dc characteristics, ac characteristi cs (prom mode) 17.6.1 read operat ion in prom mode note: tcyc = 250 ns at f clk = 16 mhz (v ss = 0 v, topr = ? 40 to 85 c) parameter symbol condition min typ. max unit high level input voltage (ttl) v ih4 v cc 0.7 ? v cc v low level input voltage (ttl) v il4 0? v cc 0.12 power supply v cc 4.75 5.0 5.25 program power supply v pp v cc - 0.6 v cc v cc + 0.6 address set-up time t asu 250 ? ? ns program access time t acc v cc = 5.0 0.25 v ? 5tcyc + 300 ? ns a0 ~ a15 d0 ~ d7 do high-z xin dids ah? ah al ce oe t acc t asu
page 143 TMP88PH40MG 17.6.2 program ope ration (high-speed) note 1: the power supply of v pp (12.75 v) must be set power-on at the same time or the later time for a power sup- ply of v cc and must be clear power-on at the same time or early time for a power supply of v cc . note 2: the pull-up/pull-dow n device on the condition of v pp = 12.75 v 0.25 v causes a damage for the device. do not pull-up/pull-down at programming. note 3: use the recommended adapter and mode. using other than the above condition ma y cause the trouble of the writting. (topr = 25 5 c) parameter symbol condition min typ. max unit high level input voltage (ttl) v ih4 v cc 0.7 ? v cc v low level input voltage (ttl) v il4 0? v cc 0.12 power supply v cc 6.0 6.25 6.5 program power supply v pp 12.5 12.75 13.0 pulse width of initializing program t pw v cc = 6.25 v 0.25 v v pp = 12.75v 0.25 v 0.095 0.1 0.105 ms t pw a0 ~ a15 d0 ~ d7 dids do ah al pgm oe program verify di ) do: data output (d0~d7), al: lower address input (a0~a7) di: data input (d0~d7), ah: upper address input (a8~a15)
page 144 17. electrical characteristics 17.8 handling precaution TMP88PH40MG 17.7 recommended osc illation conditions note 1: to ensure stable oscillation, the re sonator position, load capacitance, etc. must be appropriate. because these factors are greatly affected by board patterns, please be sure to evaluate operation on the board on which the device will actually be mounted. note 2: for the resonators to be used with toshiba microcontroll ers, we recommend ceramic resonators manufactured by murata manufacturing co., ltd. for details, please visit the website of murata at the following url: http://www.murata.com 17.8 handling precaution - the solderability test conditions for lead-free produc ts (indicated by the suffix g in product name) are shown below. 1. when using the sn-37pb solder bath solder bath temperature = 230 c dipping time = 5 seconds number of times = once r-type flux used 2. when using the sn-3.0ag-0.5cu solder bath solder bath temperature = 245 c dipping time = 5 seconds number of times = once r-type flux used note: the pass criteron of the above test is as follows: solderability rate until forming 95 % - when using the device (oscillator) in plac es exposed to high electric fields such as cathode-ray tubes, we recommend elec- trically shielding the package in order to maintain normal operating condition.

page 145 TMP88PH40MG 18. package dimensions 28 15 0.995typ 1 14 1.27 0.2 19.0max 0.10 11.43 (450mil) 0.15 +0.08 - 0.04 0.1 +0.1 - 0.05 0.43 +0.1 - 0.06 2.4 0.2 2.7max m unit : mm 0.8 0.2 18.5 0.2 8.8 0.2 11.8 0.2 sop28-p-450-1.27b rev 01
page 146 18. package dimensions TMP88PH40MG
this is a technical document that de scribes the operating functi ons and electrical specif ications of the 8-bit microcontroller series tlcs-870/x (lsi). toshiba provides a variety of development tools a nd basic software to enable efficient software development. these development tools have specifi cations that support advances in microcomputer hardware (lsi) and can be used extensively. both the hardware and so ftware are supported continuous ly with version updates. the recent advances in cmos lsi production technology have be en phenomenal and microcomputer systems for lsi design are constant ly being improved. the products described in this document may also be revised in the future. be sure to check the latest specific ations before using. toshiba is developing highly integrated, high-perfo rmance microcomputers using advanced mos production technology and especially well proven cmos technology. we are prepared to meet the requests for custom packaging for a variet y of application areas. we are confident that our products can satisfy your application needs now and in the future.

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